Phytec phyCORE-i.MX 6, Руководство по оборудованию

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phyCORE
®
-i.MX 6 [PCM-058]
10 ©
PHYTEC Messtechnik GmbH 2016 L-808e_2
Pin # Signal ST Voltage domain Description
A1 VDD_3V3 PWR_I 3.3 V 3.3 V Primary Voltage Supply Input
A2 VDD_3V3 PWR_I 3.3 V 3.3 V Primary Voltage Supply Input
A3 VDD_3V3 PWR_I 3.3 V 3.3 V Primary Voltage Supply Input
A4 VDD_3V3 PWR_I 3.3 V 3.3 V Primary Voltage Supply Input
A5 VDD_BAT PWR_I 3.3 V Backup Voltage Supply Input
7
A6 GND - - Ground 0 V
A7 X_SD3_CMD O VDD_3V3_LOGIC uSDHC3 command
A8 X_SD3_DATA0 I/O VDD_3V3_LOGIC uSDHC3 data 0
A9 X_SD3_DATA2 I/O VDD_3V3_LOGIC uSDHC3 data 2
A10 X_SD3_DATA5 I/O VDD_3V3_LOGIC uSDHC3 data 5
A11 GND - - Ground 0 V
A12 X_SD3_DATA7 I/O VDD_3V3_LOGIC uSDHC3 data 7
A13 X_SD3_RESET O VDD_3V3_LOGIC uSDHC3 reset
A14 X_SD1_DATA0 I/O VDD_3V3_LOGIC uSDHC1 data 0
A15 X_SD1_DATA2 I/O VDD_3V3_LOGIC uSDHC1 data 2
A16 GND - - Ground 0 V
A17 X_UART2_RX_DATA I VDD_3V3_LOGIC UART2 serial data receive
A18 X_UART3_RX_DATA I VDD_3V3_LOGIC UART3 serial data receive
A19 X_UART3_CTS_B O VDD_3V3_LOGIC UART3 clear to send output
A20 X_UART3_RTS_B I VDD_3V3_LOGIC UART3 request to send input
8
A21 GND - - Ground 0 V
A22 X_ECSPI1_SCLK I/O VDD_3V3_LOGIC eCSPI1 clock
A23 X_ECSPI1_MOSI I/O VDD_3V3_LOGIC eCSPI1 master output/slave input
A24 X_ECSPI1_SS0 I/O VDD_3V3_LOGIC
eCSPI1 chip select 0
8
A25 X_EIM_DA13 I/O VDD_3V3_LOGIC EIM address/data 13
9; 10
A26 GND - - Ground 0 V
A27 X_CSI1_DATA12 I VDD_3V3_LOGIC IPU2_CSI1 data 12
8
A28 X_CSI1_DATA11 I VDD_3V3_LOGIC IPU2_CSI1 data 11
8
A29 X_CSI1_DATA10 I VDD_3V3_LOGIC IPU2_CSI1 data 10
A30 X_CSI1_DATA09 I VDD_3V3_LOGIC IPU2_CSI1 data 9
8
A31 GND - - Ground 0 V
A32 X_CSI1_DATA08 I VDD_3V3_LOGIC IPU2_CSI1 data 8
8
A33 X_CSI1_DATA03 I VDD_3V3_LOGIC IPU2_CSI1 data 3
8
A34 X_CSI1_DATA02 I VDD_3V3_LOGIC IPU2_CSI1 data 2
8
A35 X_CSI1_DATA_EN O VDD_3V3_LOGIC IPU2_CSI1 data enable
8
A36
GND - - Ground 0 V
Table 3: Pinout of the phyCORE-Connector X1, Row A
7
: connects to PMIC_VBBAT or VDD_MX6_SNVS via J3 ( Table 7 )