Phytec phyCORE-i.MX 6, Руководство по оборудованию

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Pin Description
©
PHYTEC Messtechnik GmbH 2016 L-808e_2
13
Pin # Signal ST Voltage Domain Description
B37 X_CSI1_DATA13 I VDD_3V3_LOGIC IPU2_CSI1 data 13
8
B38 GND - - Ground 0 V
B39 X_CSI1_DATA07 I VDD_3V3_LOGIC IPU2_CSI1 data 7
8
B40 X_CSI1_DATA06 I VDD_3V3_LOGIC IPU2_CSI1 data 6
8
B41 X_CSI1_DATA05 I VDD_3V3_LOGIC IPU2_CSI1 data 5
8
B42 X_CSI1_DATA04 I VDD_3V3_LOGIC IPU2_CSI1 data 4
8
B43 GND - - Ground 0 V
B44 X_EIM_EB1 O VDD_3V3_LOGIC EIM enable byte 1
9; 10
B45 X_ECSPI2_SCLK I/O VDD_3V3_LOGIC eCSPI2 clock
B46 X_ECSPI2_RDY I VDD_3V3_LOGIC eCSPI2 data ready
B47 X_ECSPI2_MOSI I/O VDD_3V3_LOGIC eCSPI2 master output/slave input
B48 GND - - Ground 0 V
B49 X_LCD_DATA23 O VDD_3V3_LOGIC DISP0 data 23
B50 X_LCD_DATA20 O VDD_3V3_LOGIC DISP0 data 20
B51 X_LCD_DATA18 O VDD_3V3_LOGIC DISP0 data 18
B52 X_LCD_DATA17 O VDD_3V3_LOGIC DISP0 data 17
B53 GND - - Ground 0 V
B54 X_LCD_DATA15 O VDD_3V3_LOGIC DISP0 data 15
B55 X_LCD_DATA12 O VDD_3V3_LOGIC DISP0 data 12
B56 X_LCD_DATA10 O VDD_3V3_LOGIC DISP0 data 10
B57 X_LCD_DATA09 O VDD_3V3_LOGIC DISP0 data 9
B58 GND - - Ground 0 V
B59 X_LCD_DATA07 O VDD_3V3_LOGIC DISP0 data 7
B60 X_LCD_DATA04 O VDD_3V3_LOGIC DISP0 data 4
B61 X_LCD_DATA02 O VDD_3V3_LOGIC DISP0 data 2
B62 X_LCD_DATA01 O VDD_3V3_LOGIC DISP0 data 1
B63 GND - - Ground 0 V
B64 X_LCD_CLK O VDD_3V3_LOGIC DISP0 clock
B65 X_LCD_VSYNC O VDD_3V3_LOGIC DISP0 vertical sync
B66 X_ENET_CRS_DV I VDD_ENET_IO ENET RMII carrier sense/data valid
B67 X_ENET_TX_EN O VDD_ENET_IO ENET RMII TX enable
B68 GND - - Ground 0 V
B69 X_ENET_TXD0 O VDD_ENET_IO ENET RMII transmit data 0
B70 X_ENET_TXD1 O VDD_ENET_IO ENET RMII transmit data 1
Table 4: Pinout of the phyCORE-Connector X1, Row B (continued)
8
: Special care must be taken not to override the device configuration when using this pin as input ( section 6.2 ).
9
: Special care must be taken not to override the device configuration when using this pin as input ( section 6.2 , section 10 ).