Phytec phyCORE-i.MX 6, Руководство по оборудованию

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phyCORE
®
-i.MX 6 [PCM-058]
46 ©
PHYTEC Messtechnik GmbH 2016 L-808e_2
13 Display Interfaces
13.1 Parallel Display Interface
The signals from the LCD interface of the i.MX 6 are brought out at the phyCORE-Connector
X1. Thus an LCD interface with up to 24-bit bus width can be connected directly to the
phyCORE-i.MX 6. The table below shows the location of the applicable interface signals.
Pin # Signal ST Voltage Domain Description
X1A47 X_LCD_DATA22 O VDD_3V3_LOGIC DISP0 data 22
X1A48 X_LCD_DATA21 O VDD_3V3_LOGIC DISP0 data 21
X1A49 X_LCD_DATA19 O VDD_3V3_LOGIC DISP0 data 19
X1A50 X_LCD_DATA16 O VDD_3V3_LOGIC DISP0 data 16
X1A52 X_LCD_DATA14 O VDD_3V3_LOGIC DISP0 data 14
X1A53 X_LCD_DATA13 O VDD_3V3_LOGIC DISP0 data 13
X1A54 X_LCD_DATA11 O VDD_3V3_LOGIC DISP0 data 11
X1A55 X_LCD_DATA08 O VDD_3V3_LOGIC DISP0 data 8
X1A57 X_LCD_DATA06 O VDD_3V3_LOGIC DISP0 data 6
X1A58 X_LCD_DATA05 O VDD_3V3_LOGIC DISP0 data 5
X1A59 X_LCD_DATA03 O VDD_3V3_LOGIC DISP0 data 3
X1A60 X_LCD_DATA00 O VDD_3V3_LOGIC DISP0 data 0
X1A62 X_LCD_ENABLE O VDD_3V3_LOGIC DISP0 enable
X1A63 X_LCD_HSYNC O VDD_3V3_LOGIC DISP0 horizontal sync
X1A64 X_LCD_RESET O VDD_3V3_LOGIC DISP0 reset
X1B49 X_LCD_DATA23 O VDD_3V3_LOGIC DISP0 data 23
X1B50 X_LCD_DATA20 O VDD_3V3_LOGIC DISP0 data 20
X1B51 X_LCD_DATA18 O VDD_3V3_LOGIC DISP0 data 18
X1B52 X_LCD_DATA17 O VDD_3V3_LOGIC DISP0 data 17
X1B54 X_LCD_DATA15 O VDD_3V3_LOGIC DISP0 data 15
X1B55 X_LCD_DATA12 O VDD_3V3_LOGIC DISP0 data 12
X1B56 X_LCD_DATA10 O VDD_3V3_LOGIC DISP0 data 10
X1B57 X_LCD_DATA09 O VDD_3V3_LOGIC DISP0 data 9
X1B59 X_LCD_DATA07 O VDD_3V3_LOGIC DISP0 data 7
X1B60 X_LCD_DATA04 O VDD_3V3_LOGIC DISP0 data 4
X1B61 X_LCD_DATA02 O VDD_3V3_LOGIC DISP0 data 2
X1B62 X_LCD_DATA01 O VDD_3V3_LOGIC DISP0 data 1
X1B64 X_LCD_CLK O VDD_3V3_LOGIC DISP0 clock
X1B65 X_LCD_VSYNC O VDD_3V3_LOGIC DISP0 vertical sync
Table 25: Parallel Display Interface Signal Location