Phytec phyCORE-i.MX 6, Руководство по оборудованию

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Display Interfaces
©
PHYTEC Messtechnik GmbH 2016 L-808e_2
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13.2 LVDS Display Interface
The LVDS-Signals from both channels of the on-chip LVDS Display Bridge (LDB) on the
i.MX 6 are brought out at phyCORE-Connector X1. Thus up to two LVDS-Displays can be
connected directly to the phyCORE-i.MX 6. The location of the applicable interface signals
can be found in the table below.
Pin # Signal ST Voltage Domain Description
X1C59 X_LV LVDS_O i.MX 6 internal LVDS0 data 1+
X1C60 X_LVDS0_TX1- LVDS_O i.MX 6 internal LVDS0 data 1-
X1C61 X_LV LVDS_O i.MX 6 internal LVDS0 data 0+
X1C62 X_LVDS0_TX0- LVDS_O i.MX 6 internal LVDS0 data 0-
X1C64 X_LV LVDS_O i.MX 6 internal LVDS0 data 3+
X1C65 X_LVDS0_TX3- LVDS_O i.MX 6 internal LVDS0 data 3-
X1D58 X_LV LVDS_O i.MX 6 internal LVDS0 clock+
X1D59 X_LVDS0_CLK- LVDS_O i.MX 6 internal LVDS0 clock-
X1D60 X_LV LVDS_O i.MX 6 internal LVDS0 data 2+
X1D61 X_LVDS0_TX2- LVDS_O i.MX 6 internal LVDS0 data 2-
X1C66 X_LV LVDS_O i.MX 6 internal LVDS1 clock+
X1C67 X_LVDS1_CLK- LVDS_O i.MX 6 internal LVDS1 clock-
X1C69 X_LV LVDS_O i.MX 6 internal LVDS1 data 0+
X1C70 X_LVDS1_TX0- LVDS_O i.MX 6 internal LVDS1 data 0-
X1D63 X_LV LVDS_O i.MX 6 internal LVDS1 data 2+
X1D64 X_LVDS1_TX2- LVDS_O i.MX 6 internal LVDS1 data 2-
X1D65 X_LV LVDS_O i.MX 6 internal LVDS1 data 1+
X1D66 X_LVDS1_TX1- LVDS_O i.MX 6 internal LVDS1 data 1-
X1D68 X_LV LVDS_O i.MX 6 internal LVDS1 data 3+
X1D69 X_LVDS1_TX3- LVDS_O i.MX 6 internal LVDS1 data 3-
Table 26: LVDS Display Interface Signal Location
13.3 Supplementary Signals
Pin # Signal ST Voltage Domain Description
X1C17 X_PWM1_OUT O VDD_3V3_LOGIC
PWM1 output (e.g. to control the
brightness)
Table 27: Supplementary Signals to support the Display Connectivity