Phytec phyCORE-i.MX 6, Руководство по оборудованию

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Pin Description
©
PHYTEC Messtechnik GmbH 2016 L-808e_2
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Pin # Signal ST Voltage Domain Description
D37 X_HDMI_D0P TDMS_O i.MX 6 internal HDMI data0+
D38 X_HDMI_D0M TDMS_O i.MX 6 internal HDMI data0-
D39 X_HDMI_DDC_SCL I/O VDD_3V3_LOGIC HDMI DDC clock
D40 X_CSI0_DAT19 I VDD_3V3_LOGIC IPU1_CSI0 data 19
D41 X_CSI0_DAT17 I VDD_3V3_LOGIC IPU1_CSI0 data 17
D42 GND - - Ground 0 V
D43 X_CSI0_DAT15 I VDD_3V3_LOGIC IPU1_CSI0 data 15
D44 X_CSI0_DAT13 I VDD_3V3_LOGIC IPU1_CSI0 data 13
D45 X_CSI0_DAT11 I VDD_3V3_LOGIC IPU1_CSI0 data 11
D46 X_CSI0_DAT9 I VDD_3V3_LOGIC IPU1_CSI0 data 9
D47 X_CSI0_DAT7 I VDD_3V3_LOGIC IPU1_CSI0 data 7
D48 X_CSI0_VSYNC I VDD_3V3_LOGIC IPU1_CSI0 vertical sync
D49 GND - - Ground 0 V
D50 X_CSI0_DATA_EN O VDD_3V3_LOGIC IPU1_CSI0 data enable
D51 X_CSI0_HSYNC I VDD_3V3_LOGIC IPU1_CSI0 horizontal sync
D52 X_AUD5_RXD I/O VDD_3V3_LOGIC I
2
S AUD5 receive data
D53 X_AUD5_TXC I/O VDD_3V3_LOGIC I
2
S AUD5 transmit clock
D54 X_AUD5_TXFS I/O VDD_3V3_LOGIC I
2
S AUD5 frame sync
D55 GND - - Ground 0 V
D56 X_AUD5_TXD I/O VDD_3V3_LOGIC I
2
S AUD5 transmit data
D57 X_FLEXCAN1_RX I VDD_3V3_LOGIC FLEXCAN1 receive
D58 X_LV LVDS_O i.MX 6 internal LVDS0 clock+
D59 X_LVDS0_CLK- LVDS_O i.MX 6 internal LVDS0 clock-
D60 X_LV LVDS_O i.MX 6 internal LVDS0 data 2+
D61 X_LVDS0_TX2- LVDS_O i.MX 6 internal LVDS0 data 2-
D62 GND - - Ground 0 V
D63 X_LV LVDS_O i.MX 6 internal LVDS1 data 2+
D64 X_LVDS1_TX2- LVDS_O i.MX 6 internal LVDS1 data 2-
D65 X_LV LVDS_O i.MX 6 internal LVDS1 data 1+
D66 X_LVDS1_TX1- LVDS_O i.MX 6 internal LVDS1 data 1-
D67 GND - - Ground 0 V
D68 X_LV LVDS_O i.MX 6 internal LVDS1 data 3+
D69 X_LVDS1_TX3- LVDS_O i.MX 6 internal LVDS1 data 3-
D70 X_TAMPER/ENET_RXC I VDD_3V3_LOGIC
Tamper or ENET_RXC signal of
i.MX 6
11
Table 6: Pinout of the phyCORE-Connector X1, Row D (continued)
11
: selection of either Tamper, or ENET_RXC signal can be done with jumper J6 ( Table 7 )