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136
Open-collector Input
When connected with open collector output, insert a current limit resistor as shown below.
Controller side
Servo Driver side
When Vcc = 5 V: R = 0
Ω
When Vcc = 12 V:R = 750
Ω
When Vcc = 24 V:R = 1.6 k
Ω
220
Ω
R
+
–
+
–
Vcc
w
Deviation Counter Reset (5, 6: +ECRST/–ECRST)
The contents of the deviation counter will be reset and the position loop will be disabled when the devi-
ation counter reset signal turns ON.
The deviation counter reset signal must be input for at least 20
µ
s to be effective. The counter may or
may not be reset if the input signal is less than 20
µ
s.
The setting of Cn-02 bit No. A determines whether setting is performed on the high signal level or on the
rising edge of the signal.
•
+Feed Pulse/Reverse Pulse/90
°
Differential Pulse A Phase (CN1-1: +PULS/+CW/+A)
–Feed Pulse/Reverse Pulse/90
°
Differential Pulse A Phase (CN1-2: –PULS/–CW/–A)
+Direction Signal/Forward Pulse/90
°
Differential Pulse B Phase (CN1-3: +SIGN/+CCW/+B)
–Direction Signal/Forward Pulse/90
°
Differential Pulse B Phase (CN1-4: –SIGN/–CCW/–B)
The functions of the above pulses depend on the command pulse mode and command pulse logic
setting.
•
Command Pulse Mode (Cn-02 bit nos. 5, 4, 3)
Cn-02 bit nos. 5, 4, 3 = 0, 0, 0
Feed pulses and direction signal
Cn-02 bit nos. 5, 4, 3 = 0, 0, 1
Forward pulse and reverse pulse (factory default)
Cn-02 bit nos. 5, 4, 3 = 0, 1, 0
90
°
differential phase (A and B phases) signal (1X)
Cn-02 bit nos. 5, 4, 3 = 0, 1, 1
90
°
differential phase (A and B phases) signal (2x)
Cn-02 bit nos. 5, 4, 3 = 1, 0, 0
90
°
differential phase (A and B phases) signal (4X)
•
Command Pulse Logic Reversal (Cn-02 bit no. d)
Cn-02 bit no. d = 0
Positive logic
Cn-02 bit no. d = 1
Negative logic
Specifications
Chapter 5
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