NXP Semiconductors SAFE ASSURE Qorivva MPC5601P, Справочное руководство

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Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5602P Microcontroller Reference Manual, Rev. 4
862 Freescale Semiconductor
35.8.3.1 Selecting an IEEE 1149.1-2001 register
Access to the JTAGC data registers is done by loading the instruction register with any of the JTAGC
instructions while the JTAGC is enabled. Instructions are shifted in via the select-IR-scan path and loaded
in the update-IR state. At this point, all data register access is performed via the select-DR-scan path.
The select-DR-scan path reads or writes the register data by shifting in the data (LSB first) during the
shift-DR state. When reading a register, the register value is loaded into the IEEE 1149.1-2001 shifter
during the capture-DR state. When writing a register, the value is loaded from the IEEE 1149.1-2001
shifter to the register during the update-DR state. When reading a register, there is no requirement to shift
out the entire register contents. Shifting can be terminated after fetching the required number of bits.
35.8.4 JTAGC instructions
This section gives an overview of each instruction. Refer to the IEEE 1149.1-2001 standard for more
details.
The JTAGC implements the IEEE 1149.1-2001 defined instructions listed in Table 35-3 .
Table 35-3. JTAG instructions
Instruction Code[4:0] Instruction summary
IDCODE 00001 Selects device identification register for shift
SAMPLE/PRELOAD 00010 Selects boundary scan register for shifting, sampling, and
preloading without disturbing functional operation
SAMPLE 00011 Selects boundary scan register for shifting and sampling without
disturbing functional operation
EXTEST 00100 Selects boundary scan register while applying preloaded values to
output pins and asserting functional reset
HIGHZ 01001 Selects bypass register while tristating all output pins and
asserting functional reset
CLAMP 01100 Selects bypass register while applying preloaded values to output
pins and asserting functional reset
ACCESS_AUX_TAP_NPC 10000 Grants the Nexus port controller (NPC) ownership of the TAP
ACCESS_AUX_TAP_CORE0 10001 Enables access to Core_0 TAP controller
ACCESS_AUX_TAP_CORE1 11001 Enables access to Core_1 TAP controller
ACCESS_AUX_TAP_NASPS_
0
10111 Selects the ACCESS_AUX_NASPS_0 configuration that connects
the auxiliary TAP interface to the Nexus SRAM Port sniffer
connected between the XBAR_0 and the SRAMC_0
ACCESS_AUX_TAP_NASPS_
1
11000 Selects the ACCESS_AUX_NASPS_1 configuration that connects
the auxiliary TAP interface to the Nexus SRAM Port sniffer
connected between the XBAR_0 and the SRAMC_1
BYPASS 11111 Selects bypass register for data operations