NXP Semiconductors SAFE ASSURE Qorivva MPC5601P, Справочное руководство

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Chapter 17 Flash Memory
MPC5602P Microcontroller Reference Manual, Rev. 4
358 Freescale Semiconductor
Table 17-23. UT0 field descriptions
Field Description
UTE
0
User Test Enable
This status bit indicates when User Test is enabled. All bits in UT0–2 and UMISR0–4 are locked
when this bit is 0.
This bit is not writeable to a 1, but may be cleared. The reset value is 0.
The method to set this bit is to provide a password, and if the password matches, the UTE bit is set
to reflect the status of enabled, and is enabled until it is cleared by a register write.
For UTE the password 0xF9F9_9999 must be written to the UT0 register.
1:7 Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
DSI7-0
8:15
Data Syndrome Input 7–0
These bits represent the input of Syndrome bits of ECC logic used in the ECC Logic Check. The
DSI7–0 bits correspond to the 8 syndrome bits on a double word.
These bits are not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return
indeterminate data, and writes have no effect.
0 The syndrome bit is forced at 0.
1 The syndrome bit is forced at 1.
16:24 Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
25 Reserved (Read/Write)
This bit can be written and its value can be read back, but there is no function associated.
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
MRE
26
Margin Read Enable
MRE enables margin reads to be done. This bit, combined with MRV, enables regular user mode
reads to be replaced by margin reads.
Margin reads are only active during Array Integrity Checks; Normal user reads are not affected by
MRE.
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
0 Margin reads are disabled. All reads are User mode reads.
1 Margin reads are enabled.
MRV
27
Margin Read Value
If MRE is high, MRV selects the margin level that is being checked. Margin can be checked to an
erased level (MRV = 1) or to a programmed level (MRV = 0).
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
0 Zero’s (programmed) margin reads are requested (if MRE = 1).
1 One’s (erased) margin reads are requested (if MRE = 1).
EIE
28
ECC data Input Enable
EIE enables the ECC Logic Check operation to be done.
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
0 ECC Logic Check is disabled.
1 ECC Logic Check is enabled.