NXP Semiconductors SAFE ASSURE Qorivva MPC5601P, Справочное руководство

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Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor 865
35.9 e200z0 OnCE controller
The e200z0 core OnCE controller supports a complete set of Nexus 1 debug. A complete discussion of the
e200z0 OnCE debug features is available in the core reference manual.
35.9.1 e200z0 OnCE controller block diagram
Figure 35-6 is a block diagram of the e200z0 OnCE block.
Figure 35-6. e200z0 OnCE block diagram
35.9.2 e200z0 OnCE controller functional description
The functional description for the e200z0 OnCE controller is the same as for the JTAGC, with the
differences described as follows.
35.9.2.1 Enabling the TAP controller
To access the e200z0 OnCE controller, the proper JTAGC instruction needs to be loaded in the JTAGC
instruction register, as discussed in
Section 35.5.2.2, “TAP sharing mode. The e200z0 OnCE TAP
controller may either be accessed independently or chained with the e200z1 OnCE TAP controller, such
that the TDO output of the e200z1 TAP controller is fed into the TDI input of the e200z0 TAP controller.
The chained configuration allows commands to be loaded into both core’s OnCE registers in one shift
operation, so that both cores can be sent a GO command at the same time for example.
TCK
e200z0_TMS
TDI
Test Access Port (TAP)
e200z0_TDO
Bypass Register
External Data Register
Controller
TAP Instruction Register
OnCE Mapped Debug Registers
Auxiliary Data Register
e200z0_TRST
(OnCE OCMD)
TDO Mux
Control
{
From
JTAGC
(to JTAGC)