NXP Semiconductors SAFE ASSURE Qorivva MPC5601P, Справочное руководство

Страница: 400 / 954

Chapter 18 Enhanced Direct Memory Access (eDMA)
MPC5602P Microcontroller Reference Manual, Rev. 4
400 Freescale Semiconductor
18.5.2.17 Transfer Control Descriptor (TCD)
Each channel requires a 256-bit transfer control descriptor for defining the desired data movement
operation. The channel descriptors are stored in the local memory in sequential order: channel 0,
channel 1,... channel 15. The definitions of the TCD are presented as 23 variable-length fields.
Table 18-18 defines the fields of the basic TCD structure.
Table 18-18. TCD n 32-bit memory structure
eDMA Bit Offset
Bit
Length
TCD n Field Name
TCD n
Abbreviation
Word #
(32 × n ) + 0 32 Source address SADDR Word 0
(32 × n ) + 32 5 Source address modulo SMOD Word 1
(32 × n ) + 37 3 Source data transfer size SSIZE
(32 × n ) + 40 5 Destination address modulo DMOD
(32 × n ) + 45 3 Destination data transfer size DSIZE
(32 × n ) + 48 16 Signed Source Address Offset SOFF
(32 × n ) + 64 32 Inner minor byte count NBYTES Word 2
(32 × n ) + 96 32 Last Source Address Adjustment SLAST Word 3
(32 × n ) +
128
32 Destination Address DADDR Word 4
(32 × n ) +
160
1 Channel-to-channel Linking on Minor Loop
Complete CITER.E_LINK Word 5
(32 × n ) +
161
6 Current Major Iteration Count or
Link Channel Number CITER or
CITER.LINKCH
(32 × n ) +
167
9 Current Major Iteration Count CITER
(32 × n ) +
176
16 Destination Address Offset (Signed) DOFF
(32 × n ) +
192
32 Last Destination Address Adjustment /
Scatter Gather Address DLAST_SGA Word 6