Chapter 24 Cross Triggering Unit (CTU)
MPC5602P Microcontroller Reference Manual, Rev. 4
630
Freescale Semiconductor
24.8.3
Trigger x Compare Register (TxCR,
x
= 0...7)
24.8.4
TGS Counter Compare Register (TGSCCR)
Table 24-9. TGSCR field descriptions
Field
Description
ET_TM
This bit enables toggle mode for external triggers.
PRES
TGS and SU prescaler selection bits
00 1
01 2
10 3
11 4
MRS_SM
Master Reload Selection in Sequential Mode (5 bits to select one of 32 inputs)
TGS_M
Trigger Generator Subunit Mode
0 Triggered Mode
1 Sequential Mode
Address: Base + 0x0006 (T0CR)
Base + 0x0008 (T1CR)
Base + 0x000A (T2CR)
Base + 0x000C (T3CR)
Base + 0x000E (T4CR)
Base + 0x0010 (T5CR)
Base + 0x0012 (T6CR)
Base + 0x0014 (T7CR)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
TxCRV
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 24-11. Trigger x Compare Register (TxCR,
x
= 0...7)
Table 24-10. TxCR field descriptions
Field
Description
TxCRV
Trigger x Compare Register Value
Address: Base + 0x0016
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
TGSCCV
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 24-12. TGS Counter Compare Register (TGSCCR)
Table 24-11. TGSCCR field format
Field
Description
TGSCCV
TGS Counter Compare Value
Содержание SAFE ASSURE Qorivva MPC5601P
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Страница 708: ...Chapter 25 FlexPWM MPC5602P Microcontroller Reference Manual Rev 4 708 Freescale Semiconductor ...
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