NXP Semiconductors MC9S12VRP64, Руководство владельца

Страница: 225 / 555

S12S Debug Module (S12DBGV2)
MC9S12VRP Family Reference Manual Rev. 1.3
NXP Semiconductors 225
Field2 Bits in Normal and Loop1 Modes
6.4.5.4 Trace Buffer Organization (Compressed Pure PC mode)
Table 6-40. Trace Buffer Organization Example (Compressed PurePC mode)
Table 6-38. Field Descriptions
Bit Description
3
CSZ
Access Type Indicator — This bit indicates if the access was a byte or word size when tracing in Detail Mode
0 Word Access
1 Byte Access
2
CRW
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access when tracing in Detail Mode.
0 Write Access
1 Read Access
1
ADDR[17]
Address Bus bit 17 — Corresponds to system address bus bit 17.
0
ADDR[16]
Address Bus bit 16 — Corresponds to system address bus bit 16.
Bit 3 Bit 2 Bit 1 Bit 0
CSD CVA PC17 PC16
Figure 6-26. Information Bits PCH
Table 6-39. PCH Field Descriptions
Bit Description
3
CSD
Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored
address is a source or destination address. This bit has no meaning in Compressed Pure PC mode.
0 Source Address
1 Destination Address
2
CVA
Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector
address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set.
This bit has no meaning in Compressed Pure PC mode.
0 Non-Vector Destination Address
1 Vector Destination Address
1
PC17
Program Counter bit 17 — In Normal and Loop1 mode this bit corresponds to program counter bit 17.
0
PC16
Program Counter bit 16 — In Normal and Loop1 mode this bit corresponds to program counter bit 16.
Mode
Line
Number
2-bits 6-bits 6-bits 6-bits
Field 3 Field 2 Field 1 Field 0