NXP Semiconductors MC9S12VRP64, Руководство владельца

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Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12VRP Family Reference Manual Rev. 1.3
280 NXP Semiconductors
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9.3.2.5 PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
Section 9.4.2.5, “Left Aligned Outputs” and Section 9.4.2.6, “Center Aligned Outputs” for a more detailed
description of the PWM output modes.
Read: Anytime
Write: Anytime
NOTE
Write these bits only when the corresponding channel is disabled.
Table 9-7. PWMPRCLK Field Descriptions
Field Description
6–4
PCKB[2:0]
Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for all channels. These
three bits determine the rate of clock B, as shown in Table 9-8 .
2–0
PCKA[2:0]
Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for all channels. These
three bits determine the rate of clock A, as shown in Table 9-8 .
Table 9-8. Clock A or Clock B Prescaler Selects
PCKA/B2 PCKA/B1 PCKA/B0 Value of Clock A/B
0 0 0 bus clock
0 0 1 bus clock / 2
0 1 0 bus clock / 4
0 1 1 bus clock / 8
1 0 0 bus clock / 16
1 0 1 bus clock / 32
1 1 0 bus clock / 64
1 1 1 bus clock / 128
7 6 5 4 3 2 1 0
R
CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
W
Reset 0 0 0 0 0 0 0 0
Figure 9-7. PWM Center Align Enable Register (PWMCAE)
Table 9-9. PWMCAE Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field Description
7–0
CAE[7:0]
Center Aligned Output Modes on Channels 7–0
0 Channels 7–0 operate in left aligned output mode.
1 Channels 7–0 operate in center aligned output mode.