S12S Debug Module (S12DBGV2)
MC9S12VRP Family Reference Manual Rev. 1.3
226
NXP Semiconductors
NOTE
Configured for end aligned triggering in compressed PurePC mode, then
after rollover it is possible that the oldest base address is overwritten. In this
case all entries between the pointer and the next base address have lost their
base address following rollover. For example in
rollover has occurred, Line 1, PC1, is overwritten with a new entry. Thus the
entries on Lines 2 and 3 have lost their base address. For reconstruction of
program flow the first base address following the pointer must be used, in
the example, Line 4. The pointer points to the oldest entry, Line 2.
Field3 Bits in Compressed Pure PC Modes
Each time that PC[17:6] differs from the previous base PC[17:6], then a new base address is stored. The
base address zero value is the lowest address in the 64 address range
The first line of the trace buffer always gets a base PC address, this applies also on rollover.
6.4.5.5
Reading Data from Trace Buffer
The data stored in the Trace Buffer can be read provided the DBG module is not armed, is configured for
tracing (TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer
is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word
write to DBGTB when the module is disarmed.
The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or
misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of
valid lines can be determined. DBGCNT does not decrement as data is read.
Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the
pointer points to the oldest data entry, thus if no rollover has occurred, the pointer points to line0, otherwise
it points to the line with the oldest entry. In compressed Pure PC mode on rollover the line with the oldest
Compressed
Pure PC Mode
Line 1
00
PC1 (Initial 18-bit PC Base Address)
Line 2
11
PC4
PC3
PC2
Line 3
01
0
0
PC5
Line 4
00
PC6 (New 18-bit PC Base Address)
Line 5
10
0
PC8
PC7
Line 6
00
PC9 (New 18-bit PC Base Address)
Table 6-41. Compressed Pure PC Mode Field 3 Information Bit Encoding
INF1
INF0
TRACE BUFFER ROW CONTENT
0
0
Base PC address TB[17:0] contains a full PC[17:0] value
0
1
Trace Buffer[5:0] contain incremental PC relative to base address zero value
1
0
Trace Buffer[11:0] contain next 2 incremental PCs relative to base address zero value
1
1
Trace Buffer[17:0] contain next 3 incremental PCs relative to base address zero value
Содержание MC9S12VRP64
Страница 16: ...MC9S12VRP Family Reference Manual Rev 1 3 16 NXP Semiconductors ...
Страница 46: ...Device Overview S12VRP Series MC9S12VRP Family Reference Manual Rev 1 3 46 NXP Semiconductors ...
Страница 92: ...Port Integration Module S12VRPPIMV1 MC9S12VRP Family Reference Manual Rev 1 3 92 NXP Semiconductors ...
Страница 106: ...S12G Memory Map Controller S12GMMCV1 MC9S12VRP Family Reference Manual Rev 1 3 106 NXP Semiconductors ...
Страница 192: ...Background Debug Module S12SBDMV1 MC9S12VRP Family Reference Manual Rev 1 3 192 NXP Semiconductors ...
Страница 236: ...S12S Debug Module S12DBGV2 MC9S12VRP Family Reference Manual Rev 1 3 236 NXP Semiconductors ...
Страница 244: ...Interrupt Module S12SINTV1 MC9S12VRP Family Reference Manual Rev 1 3 244 NXP Semiconductors ...
Страница 340: ...Serial Communication Interface S12SCIV6 MC9S12VRP Family Reference Manual Rev 1 3 340 NXP Semiconductors ...
Страница 358: ...Timer Module TIM16B2CV3 MC9S12VRP Family Reference Manual Rev 1 3 358 NXP Semiconductors ...
Страница 424: ...LIN Physical Layer S12LINPHYV2 MC9S12VRP Family Reference Manual Rev 1 3 424 NXP Semiconductors ...
Страница 436: ...Supply Voltage Sensor BATSV2 MC9S12VRP Family Reference Manual Rev 1 3 436 NXP Semiconductors ...
Страница 488: ...64 KByte Flash Module S12FTMRG64K4KV2 MC9S12VRP Family Reference Manual Rev 1 3 488 NXP Semiconductors ...
Страница 528: ...NVM Electrical Parameters MC9S12VRP Family Reference Manual Rev 1 3 528 NXP Semiconductors ...
Страница 529: ...MC9S12VRP Family Reference Manual Rev 1 3 NXP Semiconductors 529 Appendix J Package Information ...
Страница 530: ...Package Information MC9S12VRP Family Reference Manual Rev 1 3 530 NXP Semiconductors ...
Страница 531: ...Package Information MC9S12VRP Family Reference Manual Rev 1 3 NXP Semiconductors 531 ...
Страница 532: ...Package Information MC9S12VRP Family Reference Manual Rev 1 3 532 NXP Semiconductors ...