S12S Debug Module (S12DBGV2)
MC9S12VRP Family Reference Manual Rev. 1.3
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and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and
the debug module is disarmed.
6.4.4.1
Final State
On entering Final State a trigger may be issued to the trace buffer according to the trace alignment control
as defined by the TALIGN bit (see
Section 6.3.2.3, “Debug Trace Control Register (DBGTCR)”
). If the
TSOURCE bit in DBGTCR is clear then the trace buffer is disabled and the transition to Final State can
only generate a breakpoint request. In this case or upon completion of a tracing session when tracing is
enabled, the ARM bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If
tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor
breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug
module is disarmed.
6.4.5
Trace Buffer Operation
The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information
in the RAM array in a circular buffer format. The system accesses the RAM array through a register
window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 20-bit trace buffer
line is read, an internal pointer into the RAM increments so that the next read receives fresh information.
Data is stored in the format shown in
and
. After each store the counter register
DBGCNT is incremented. Tracing of CPU activity is disabled when the BDM is active. Reading the trace
buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented.
6.4.5.1
Trace Trigger Alignment
Using the TALIGN bit (see
Section 6.3.2.3, “Debug Trace Control Register (DBGTCR)
align the trigger with the end or the beginning of a tracing session.
If end alignment is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the
transition to Final State signals the end of the tracing session. Tracing with Begin-Trigger starts at the
opcode of the trigger. Using end alignment or when the tracing is initiated by writing to the TRIG bit whilst
configured for begin alignment, tracing starts in the second cycle after the DBGC1 write cycle.
6.4.5.1.1
Storing with Begin Trigger Alignment
Storing with begin alignment, data is not stored in the Trace Buffer until the Final State is entered. Once
the trigger condition is met the DBG module remains armed until 64 lines are stored in the Trace Buffer.
If the trigger is at the address of the change-of-flow instruction the change of flow associated with the
trigger is stored in the Trace Buffer. Using begin alignment together with tagging, if the tagged instruction
is about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is
generated, thus the breakpoint does not occur at the tagged instruction boundary.
6.4.5.1.2
Storing with End Trigger Alignment
Storing with end alignment, data is stored in the Trace Buffer until the Final State is entered, at which point
the DBG module becomes disarmed and no more data is stored. If the trigger is at the address of a change
Содержание MC9S12VRP64
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Страница 46: ...Device Overview S12VRP Series MC9S12VRP Family Reference Manual Rev 1 3 46 NXP Semiconductors ...
Страница 92: ...Port Integration Module S12VRPPIMV1 MC9S12VRP Family Reference Manual Rev 1 3 92 NXP Semiconductors ...
Страница 106: ...S12G Memory Map Controller S12GMMCV1 MC9S12VRP Family Reference Manual Rev 1 3 106 NXP Semiconductors ...
Страница 192: ...Background Debug Module S12SBDMV1 MC9S12VRP Family Reference Manual Rev 1 3 192 NXP Semiconductors ...
Страница 236: ...S12S Debug Module S12DBGV2 MC9S12VRP Family Reference Manual Rev 1 3 236 NXP Semiconductors ...
Страница 244: ...Interrupt Module S12SINTV1 MC9S12VRP Family Reference Manual Rev 1 3 244 NXP Semiconductors ...
Страница 340: ...Serial Communication Interface S12SCIV6 MC9S12VRP Family Reference Manual Rev 1 3 340 NXP Semiconductors ...
Страница 358: ...Timer Module TIM16B2CV3 MC9S12VRP Family Reference Manual Rev 1 3 358 NXP Semiconductors ...
Страница 424: ...LIN Physical Layer S12LINPHYV2 MC9S12VRP Family Reference Manual Rev 1 3 424 NXP Semiconductors ...
Страница 436: ...Supply Voltage Sensor BATSV2 MC9S12VRP Family Reference Manual Rev 1 3 436 NXP Semiconductors ...
Страница 488: ...64 KByte Flash Module S12FTMRG64K4KV2 MC9S12VRP Family Reference Manual Rev 1 3 488 NXP Semiconductors ...
Страница 528: ...NVM Electrical Parameters MC9S12VRP Family Reference Manual Rev 1 3 528 NXP Semiconductors ...
Страница 529: ...MC9S12VRP Family Reference Manual Rev 1 3 NXP Semiconductors 529 Appendix J Package Information ...
Страница 530: ...Package Information MC9S12VRP Family Reference Manual Rev 1 3 530 NXP Semiconductors ...
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