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UM10375
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© NXP B.V. 2011. All rights reserved.
User manual
Rev. 3 — 14 June 2011
57 of 368
NXP Semiconductors
UM10375
Chapter 5: LPC13xx Power profiles
CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such
as overall current consumption and/or power budget reasons).
CPU_FREQ_GTE helps applications that need a minimum level of CPU processing
capabilities.
CPU_FREQ_APPROX results in a system clock that is as close as possible to the
requested value (it may be greater than or less than the requested value).
If an illegal mode is specified,
set_pll
returns PLL_INVALID_MODE. If the expected
system clock is out of the range supported by this routine,
set_pll
returns
PLL_FREQ_NOT_FOUND. In these cases the current PLL setting is not changed and
Param0
is returned as
Result1
.
5.5.1.3 Param3: system PLL lock time-out
It should take no more than 100
s for the system PLL to lock if a valid configuration is
selected. If
Param3
is zero,
set_pll
will wait indefinitely for the PLL to lock. A non-zero
value indicates how many times the code will check for a successful PLL lock event
before it returns PLL_NOT_LOCKED. In this case the PLL settings are unchanged and
Param0
is returned as
Result1
.
Remark:
The time it takes the PLL to lock depends on the selected PLL input clock
source (IRC/system oscillator) and its characteristics. The selected source can
experience more or less jitter depending on the operating conditions such as power
supply and/or ambient temperature. This is why it is suggested that when a good known
clock source is used and a PLL_NOT_LOCKED response is received, the set_pll routine
should be invoked several times before declaring the selected PLL clock source invalid.
Hint:
setting
Param3
equal to the system PLL frequency [Hz] divided by 10000 will
provide more than enough PLL lock-polling cycles.
5.5.1.4 Code examples
The following examples illustrate some of the features of
set_pll
discussed above.
5.5.1.4.1
Invalid frequency (device maximum clock rate exceeded)
command[0] = 12000;
command[1] = 84000;
command[2] = CPU_FREQ_EQU;
command[3] = 0;
(*rom)->pWRD->set_pll(command, result);
The above code specifies a 12 MHz PLL input clock and a system clock of exactly
84 MHz. The application was ready to infinitely wait for the PLL to lock. But the expected
system clock of 84 MHz exceeds the maximum of 72 MHz. Therefore
set_pll
returns
PLL_INVALID_FREQ in
result[0]
and 12000 in
result[1]
without changing the PLL
settings.
5.5.1.4.2
Invalid frequency selection (system clock divider restrictions)
command[0] = 12000;
command[1] = 40;
command[2] = CPU_FREQ_LTE;