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UM10375

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2011. All rights reserved.

User manual

Rev. 3 — 14 June 2011 

164 of 368

NXP Semiconductors

UM10375

Chapter 10: LPC13xx USB device controller

For non-isochronous endpoints when a full data packet is received without any errors, the 
endpoint generates a request for data transfer from its FIFO by generating an interrupt to 
the system.

Isochronous endpoint will have one packet of data to be transferred in every frame. This 
requires the data transfer has to be synchronized to the USB frame rather than packet 
arrival. The 1 KHz free running clock re synchronized on the incoming SoF tokens will 
generate an interrupt every millisecond.

The data transfer follows the little endian format. The first byte received from the USB bus 
will be available in the LS byte of the receive data register.

10.13.2 Data flow from the Device to the Host

For data transfer from an endpoint to the host, the host will send an IN token to that 
endpoint. If the FIFO corresponding to the endpoint is empty, the device will return a NAK 
and will generate an interrupt (assuming the interrupt on NAK is enabled). On this 
interrupt the processor fills a packet of data in the endpoint FIFO. The next IN token that 
comes--after filling this packet--will transfer this packet to the host.

The data transfer follows the little endian format. The first byte sent on the USB bus will be 
the LS byte of the transmit data register.

Remark: 

USB is a host controlled protocol, i.e., irrespective of whether the data transfer is 

from the host to the device or from the device to the host, the transfer sequence is always 
initiated by the host. During data transfer from the device to the host, the host sends an IN 
token to the device, following which the device responds with the data.

10.13.3 Interrupt based transfer

Interrupt based data transfer is done through the interrupt issued from the USB core to the 
processor.

Reception of a valid (error-free) data packet in any of the OUT non-isochronous endpoint 
buffer generates an interrupt. Upon receiving the interrupt, the software can read the data 
using receive length and data registers. When there is no empty buffer (for a given 
non-isochronous OUT endpoint), any data arrival generates an interrupt only if Interrupt 
On NAK feature for that endpoint type is enabled and existing interrupt is cleared.

Similarly, when a packet is successfully transferred to the host from any IN 
non-isochronous endpoint buffer, an interrupt is generated. When there is no data 
available in any of the buffers (for a given non-isochronous IN endpoint), a data request 
generates an interrupt only if Interrupt On NAK feature for that endpoint type is enabled 
and existing interrupt is cleared. Upon receiving the interrupt, the software can load any 
data to be sent using transmit length and data registers.

10.13.4 Isochronous transfer

Isochronous endpoints are double-buffered and the buffer toggling will happen only on 
frame boundaries i.e., at every 1 ms. ‘Clear Buffer’ and ‘Validate Buffer’ do not cause the 
buffer to toggle.

Содержание LPC1311

Страница 1: ...42 43 User manual Rev 3 14 June 2011 User manual Document information Info Content Keywords ARM Cortex M3 microcontroller USB LPC1311 LPC1313 LPC1342 LPC1343 LPC1311 01 LPC1313 01 Abstract LPC1311 13...

Страница 2: ...le 128 Table 129 Table 134 and Table 138 Use of IRC for entering deep power down updated in Section 3 9 4 2 Enable sequence for UART clock updated in Section 12 1 Chapter 5 LPC13xx Power profiles adde...

Страница 3: ...O pins 1 2 How to read this manual This user manual describes parts LPC1311 LPC1313 LPC1342 LPC1343 Part specific features and registers are listed at the beginning of each chapter Remark The LPC13xx...

Страница 4: ...20 mA on two I2C bus pins in Fast mode Plus Integrated PMU Power Management Unit to minimize power consumption during Sleep Deep sleep and Deep power down modes Power profiles residing in boot ROM all...

Страница 5: ...y 7 7 0 85 mm n a LPC1313FHN33 01 HVQFN33 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals body 7 7 0 85 mm n a LPC1313FBD48 LQFP48 LQFP48 plastic low profile quad fl...

Страница 6: ...Semiconductors UM10375 Chapter 1 LPC13xx Introductory information LPC1342FBD48 16 kB 4 kB Device no 1 1 1 8 48 LQFP48 LPC1343FHN33 32 kB 8 kB Device no 1 1 1 8 33 HVQFN33 LPC1343FBD48 32 kB 8 kB Devic...

Страница 7: ...NTROLLER 1 I code bus D code bus system bus AHB TO APB BRIDGE HIGH SPEED GPIO CLOCK GENERATION POWER CONTROL SYSTEM FUNCTIONS XTALIN XTALOUT RESET clocks and controls SWD USB PHY 1 SSP0 10 bit ADC UAR...

Страница 8: ...ecoding for each peripheral All peripheral register addresses are 32 bit word aligned regardless of their size An implication of this is that word and half word registers must be accessed all at once...

Страница 9: ...timer 0 32 bit counter timer 1 ADC UART PMU I2C bus 10 13 reserved reserved 19 21 reserved 23 31 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved 0x0000 0000 0 GB 0 5 GB 4 GB 1 GB 0x0000...

Страница 10: ...nfiguration Rev 3 14 June 2011 User manual Table 4 USB related registers and register bits reserved for LPC1311 13 Name Access Address offset Description Register bits reserved for LPC1311 13 USBPLLCT...

Страница 11: ...s LPC1311 01 and LPC1313 01 Enabling sequence for UART clock Requirements for enabling the UART peripheral clock The UART pins must be configured in the IOCON block before the UART clock can be enable...

Страница 12: ...configuration 3 3 Pin description Table 6 shows pins that are associated with system control block functions 1 For HVQFN packages applies to P2_0 P3_2 and P3_3 only Table 6 Pin summary Pin name Pin di...

Страница 13: ...ired in a particular application Following reset the LPC131x will operate from the Internal RC oscillator until switched by software This allows systems to operate without any external crystal and the...

Страница 14: ...t part of the system configuration block USB is available in parts LPC134x only SSP1 is available on part LPC1313FBD48 only Fig 3 LPC13xx CGU block diagram SYS PLL irc_osc_clk sys_osc_clk sys_osc_clk...

Страница 15: ...R W 0x048 USB PLL clock source select 0x0000 0000 Table 20 USBPLLCLKUEN R W 0x04C USB PLL clock source update enable 0x0000 0000 Table 21 0x050 0x06C Reserved MAINCLKSEL R W 0x070 Main clock source se...

Страница 16: ...ERP0 R W 0x204 Start logic signal enable register 0 bottom 32 interrupts Table 45 STARTRSRP0CLR W 0x208 Start logic reset register 0 bottom 32 interrupts Table 46 STARTSRP0 R 0x20C Start logic status...

Страница 17: ...put frequency is multiplied up to a high frequency then divided down to provide the actual clock used by the CPU peripherals and optionally the USB subsystem Note that the USB subsystem has its own de...

Страница 18: ...sed by the USB subsystem Remark The USB PLL must be connected to the system oscillator for correct USB operation see Table 20 Table 10 System PLL control register SYSPLLCTRL address 0x4004 8008 bit de...

Страница 19: ...he PLL lock status see Section 3 11 1 6 5 PSEL Post divider ratio P The division ratio is 2 P 0x00 0x0 P 1 0x1 P 2 0x2 P 4 0x3 P 8 31 7 Reserved Do not write ones to reserved bits 0x00 Table 12 USB PL...

Страница 20: ...na 2 1 DIVSEL 7 8 kHz to 1 7 MHz nominal values Remark Any setting of the FREQSEL bits will yield a Fclkana value within 40 of the listed frequency value The watchdog oscillator is the clock source wi...

Страница 21: ...EQSEL Select watchdog oscillator analog output frequency Fclkana 0x00 0x1 0 5 MHz 0x2 0 8 MHz 0x3 1 1 MHz 0x4 1 4 MHz 0x5 1 6 MHz 0x6 1 8 MHz 0x7 2 0 MHz 0x8 2 2 MHz 0x9 2 4 MHz 0xA 2 6 MHz 0xB 2 7 MH...

Страница 22: ...12 must be toggled from LOW to HIGH for the update to take effect Remark The system oscillator must be selected if the system PLL is used to generate a 48 MHz clock to the USB block Remark When switch...

Страница 23: ...be running before the clock source is updated in the USBPLLCLKUEN register For USB operation the clock source must be switched from IRC to system oscillator with both the IRC and the system oscillato...

Страница 24: ...em PLL sys_pllclkout or the watchdog or IRC oscillators directly The main system clock clocks the core the peripherals and memories and optionally the USB block The MAINCLKUEN register see Section 3 5...

Страница 25: ...idge the AHB matrix the ARM Cortex M3 the Syscon block and the PMU This clock cannot be disabled Table 23 Main clock source update enable register MAINCLKUEN address 0x4004 8074 bit description Bit Sy...

Страница 26: ...clock for 16 bit counter timer 1 0 0 Disabled 1 Enabled 9 CT32B0 Enables clock for 32 bit counter timer 0 0 0 Disabled 1 Enabled 10 CT32B1 Enables clock for 32 bit counter timer 1 0 0 Disabled 1 Enab...

Страница 27: ...and LPC1313 01 no special enabling sequence is required 15 WDT Enables clock for WDT 0 0 Disabled 1 Enabled 16 IOCON Enables clock for IO configuration block 0 0 Disabled 1 Enabled 17 Reserved 0x00 1...

Страница 28: ...source can be either the USB PLL output or the main clock and the clock can be further divided by the USBCLKDIV register see Table 33 to obtain a 48 MHz clock The USBCLKUEN register see Section 3 5 2...

Страница 29: ...er for the update to take effect first write a zero to the USBCLKUEN register and then write a one to USBCLKUEN Remark When switching clock sources both clocks must be running before the clock source...

Страница 30: ...CLKSEL register has been written to In order for the update to take effect at the input of the watchdog timer first write a zero to the WDTCLKUEN register and then write a one to WDTCLKUEN Remark When...

Страница 31: ...h the new clock after the CLKOUTCLKSEL register has been written to In order for the update to take effect at the input of the CLKOUT pin first write a zero to the CLKCLKUEN register and then write a...

Страница 32: ...address 0x4004 8100 bit description Bit Symbol Description Reset value 11 0 CAPPIO0_11 to CAPPIO0_0 Raw reset status input PIO0_11 to PIO0_0 User implementation dependent 23 12 CAPPIO1_11 to CAPPIO1_...

Страница 33: ...reshold voltage is 2 15 V 0x2 The reset assertion threshold voltage is 2 35 V the reset de assertion threshold voltage is 2 43 V 0x3 The reset assertion threshold voltage is 2 63 V the reset de assert...

Страница 34: ...e enabled in the NVIC if the corresponding PIO pin is used to wake up the chip from Deep sleep mode 3 5 38 Start logic signal enable register 0 This STARTERP0 register enables or disables the start si...

Страница 35: ...PIO3_0 to PIO3_3 This register selects a falling or rising edge on the corresponding PIO input to produce a falling or rising clock edge respectively for the start up logic Table 46 Start logic reset...

Страница 36: ...RSRP1CLR register resets the start logic state The bit assignment is identical to Table 48 The start up logic uses the input signals to generate a clock edge for registering a start signal This clock...

Страница 37: ...ower configuration for Deep sleep mode consider the following Table 50 Start logic reset register 1 STARTRSRP1CLR address 0x4004 8218 bit description Bit Symbol Description Reset value 3 0 RSRPIO2_n S...

Страница 38: ...in in Deep sleep mode Remark Reserved bits in this register must always be written as indicated This register must be initialized correctly before entering Deep sleep mode 3 5 46 Wake up configuration...

Страница 39: ...IRC oscillator power down wake up configuration 0 0 Powered 1 Powered down 2 FLASH_PD Flash wake up configuration 0 0 Powered 1 Powered down 3 BOD_PD BOD wake up configuration 0 0 Powered 1 Powered d...

Страница 40: ...Description Reset value 0 IRCOUT_PD IRC oscillator output power down 0 0 Powered 1 Powered down 1 IRC_PD IRC oscillator power down 0 0 Powered 1 Powered down 2 FLASH_PD Flash power down 0 0 Powered 1...

Страница 41: ...1 The IRC starts up After the IRC start up time maximum of 6 s on power up the IRC provides a stable clock output 2 The boot code in the ROM starts The boot code performs the boot tasks and may jump...

Страница 42: ...ter Oneadditional threshold level can be selected to cause a forced reset of the chip on the LPC1311 13 42 43 parts Four additional threshold levels for forced reset can be selected on the LPC1311 01...

Страница 43: ...ble 10 and the SYSAHBCLKDIV register Table 24 Selected peripherals UART SSP0 1 WDT use individual peripheral clocks with their own clock dividers The peripheral clocks can be shut down through the cor...

Страница 44: ...ion in Deep sleep mode is determined by the Deep sleep power configuration setting in the PDSLEEPCFG Table 53 register The only clock source available in Deep sleep mode is the watchdog oscillator The...

Страница 45: ...c input in the NVIC the corresponding timer must be enabled in the SYSAHBCLKCTRL register and the watchdog oscillator must be running in Deep sleep mode for details see Section 3 10 3 Reset from the B...

Страница 46: ...e entire reset process Section 3 6 The minimum pulse width for the HIGH to LOW transition on the WAKEUP pin is 50 ns 1 A wake up signal is generated when a HIGH to LOW transition occurs externally on...

Страница 47: ...the corresponding match output pin to go HIGH LOW or toggle The state of the match output pin is also monitored by the start logic and can trigger a wake up interrupt if that pin is enabled in the NV...

Страница 48: ...t signal of the phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock Remark The divider values for P and M must be selected so that t...

Страница 49: ...as shown in Table 10 and Table 12 This guarantees an output clock with a 50 duty cycle Feedback divider The feedback divider s division ratio is controlled by the MSEL bits The division ratio between...

Страница 50: ...clock divider SYSAHBCLKDIV is set to one see Table 24 3 11 4 2 Power down mode In this mode the internal current reference will be turned off the oscillator and the phase frequency detector will be st...

Страница 51: ...LASHCFG register at address 0x4003 C010 This register is part of the flash controller block see Figure 2 Remark Improper setting of this register may result in incorrect operation of the LPC13xx flash...

Страница 52: ...ddress 0x4003 8000 Name Access Address offset Description Reset value PCON R W 0x000 Power control register 0x0 GPREG0 R W 0x004 General purpose register 0 0x0 GPREG1 R W 0x008 General purpose registe...

Страница 53: ...al voltage applied on pin VDD drops below 2 2 V during Deep power down the hysteresis of the WAKEUP input pin has to be disabled in this register before entering Deep power down mode in order for the...

Страница 54: ...1313 01 only LPC1300L series 5 2 Features Includes ROM based application services Power Management services Clocking services 5 3 Description The API calls to the ROM are performed by executing functi...

Страница 55: ...wer system power consumption Remark Before this routine is invoked the PLL clock source IRC system oscillator must be selected Table 18 the main clock source must be set to the input clock to the syst...

Страница 56: ...easily finds a solution when the ratio between the expected system clock and the system PLL input frequency is an integer value but it can also find solutions in other cases The system PLL input frequ...

Страница 57: ...PLL settings are unchanged and Param0 is returned as Result1 Remark The time it takes the PLL to lock depends on the selected PLL input clock source IRC system oscillator and its characteristics The s...

Страница 58: ...e PLL to lock Since there is no valid PLL setup within earlier mentioned restrictions set_pll returns PLL_FREQ_NOT_FOUND in result 0 and 12000 in result 1 without changing the PLL settings 5 5 1 4 4 S...

Страница 59: ...f interest to the application close to its optimum Remark The set_power routine was designed for systems employing the configuration of SYSAHBCLKDIV 1 System clock divider register see Table 24 and Fi...

Страница 60: ...ameter mode Param1 specifies one of four available power settings If an illegal selection is provided set_power returns PWR_INVALID_MODE and does not change the power control system PWR_DEFAULT keeps...

Страница 61: ...sult The above setup would be used in a system running at the main and system clock of 75 MHz with a need for maximum CPU processing power Since the specified 75 MHz clock is above the 72 MHz maximum...

Страница 62: ...o the CPU allows for low interrupt latency and efficient processing of late arriving interrupts Refer to the Cortex M3 Technical Reference Manual for details of NVIC operation 6 3 Features Nested Vect...

Страница 63: ...to 39 are connected to PIO3_0 to PIO3_3 1 40 0xA0 I2C0 SI state change 41 0xA4 CT16B0 Match 0 2 Capture 0 42 0xA8 CT16B1 Match 0 1 Capture 0 43 0xAC CT32B0 Match 0 3 Capture 0 44 0xB0 CT32B1 Match 0 3...

Страница 64: ...3 address space The vector table should be located on a 256 word 1024 byte boundary to insure alignment on LPC13xx family devices Refer to the ARM Cortex M3 User Guide for details of the Vector Table...

Страница 65: ...This register allows changing the interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions 0 IABR0 RO 0x300 Interrupt Active Bit Register 0 This re...

Страница 66: ...interrupt Each register contains the 5 bit priority fields for 4 interrupts 0 IPR13 RW 0x434 Interrupt Priority Registers 13 This register allows assigning a priority to each interrupt Each register c...

Страница 67: ...input interrupt enable 23 ISE_PIO1_11 PIO1_11 start logic input interrupt enable 24 ISE_PIO2_0 PIO2_0 start logic input interrupt enable 25 ISE_PIO2_1 PIO2_1 start logic input interrupt enable 26 ISE_...

Страница 68: ...9 ISE_BOD BOD interrupt enable 20 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 21 ISE_PIO_3 GPIO port 3 interrupt enable 22 ISE_PIO_2...

Страница 69: ...PIO1_7 PIO1_7 start logic input interrupt disable 20 ICE_PIO1_8 PIO1_8 start logic input interrupt disable 21 ICE_PIO1_9 PIO1_9 start logic input interrupt disable 22 ICE_PIO1_10 PIO1_10 start logic i...

Страница 70: ...2B1 interrupt disable 13 ICE_SSP0 SSP0 interrupt disable 14 ICE_UART UART interrupt disable 15 ICE_USBIRQ USB IRQ interrupt disable 16 ICE_USBFRQ USB FRQ interrupt disable 17 ICE_ADC ADC interrupt dis...

Страница 71: ...put interrupt pending set 12 ISP_PIO1_0 PIO1_0 start logic input interrupt pending set 13 ISP_PIO1_1 PIO1_1 start logic input interrupt pending set 14 ISP_PIO1_2 PIO1_2 start logic input interrupt pen...

Страница 72: ...0 PIO2_10 start logic input interrupt pending set 3 ISP_PIO2_11 PIO2_11 start logic input interrupt pending set 4 ISP_PIO3_0 PIO3_0 start logic input interrupt pending set 5 ISP_PIO3_1 PIO3_0 start lo...

Страница 73: ...nding clear 12 ICP_PIO1_0 PIO1_0 start logic input interrupt pending clear 13 ICP_PIO1_1 PIO1_1 start logic input interrupt pending clear 14 ICP_PIO1_2 PIO1_2 start logic input interrupt pending clear...

Страница 74: ...IO2_11 start logic input interrupt pending clear 4 ICP_PIO3_0 PIO3_0 start logic input interrupt pending clear 5 ICP_PIO3_1 PIO3_0 start logic input interrupt pending clear 6 ICP_PIO3_2 PIO3_0 start l...

Страница 75: ...input interrupt active 7 IAB_PIO0_7 PIO0_7 start logic input interrupt active 8 IAB_PIO0_8 PIO0_8 start logic input interrupt active 9 IAB_PIO0_9 PIO0_9 start logic input interrupt active 10 IAB_PIO0...

Страница 76: ...PIO2_11 PIO2_11 start logic input interrupt active 4 IAB_PIO3_0 PIO3_0 start logic input interrupt active 5 IAB_PIO3_1 PIO3_0 start logic input interrupt active 6 IAB_PIO3_2 PIO3_0 start logic input i...

Страница 77: ...writes and read as 0 15 13 IP_PIO0_1 PIO0_1 Interrupt Priority 0 highest priority 31 0x1F lowest priority 20 16 Unimplemented These bits ignore writes and read as 0 23 21 IP_PIO0_2 PIO0_2 Interrupt P...

Страница 78: ...rites and read as 0 15 13 IP_PIO0_9 PIO0_9 Interrupt Priority 0 highest priority 31 0x1F lowest priority 20 16 Unimplemented These bits ignore writes and read as 0 23 21 IP_PIO0_10 PIO0_10 Interrupt P...

Страница 79: ...rites and read as 0 15 13 IP_PIO1_5 PIO0_5 Interrupt Priority 0 highest priority 31 0x1F lowest priority 20 16 Unimplemented These bits ignore writes and read as 0 23 21 IP_PIO1_6 PIO0_6 Interrupt Pri...

Страница 80: ...e writes and read as 0 15 13 IP_PIO2_1 PIO2_1 Interrupt Priority 0 highest priority 31 0x1F lowest priority 20 16 Unimplemented These bits ignore writes and read as 0 23 21 IP_PIO2_2 PIO2_2 Interrupt...

Страница 81: ...rites and read as 0 15 13 IP_PIO2_9 PIO0_9 Interrupt Priority 0 highest priority 31 0x1F lowest priority 20 16 Unimplemented These bits ignore writes and read as 0 23 21 IP_PIO2_10 PIO0_10 Interrupt P...

Страница 82: ...ore writes and read as 0 15 13 IP_CT16B0 CT16B0 Interrupt Priority 0 highest priority 31 0x1F lowest priority 20 16 Unimplemented These bits ignore writes and read as 0 23 21 IP_CT16B1 CT16B1 Interrup...

Страница 83: ...lowest priority 12 8 Unimplemented These bits ignore writes and read as 0 15 13 IP_ADC ADC Interrupt Priority 0 highest priority 31 0x1F lowest priority 20 16 Unimplemented These bits ignore writes an...

Страница 84: ...lity if privileged software sets the USERSETMPEND bit in the ARM Cortex M3 CCR register Table 92 Interrupt Priority Register 14 IPR14 address 0xE000 E438 bit description Bit Symbol Description 4 0 Uni...

Страница 85: ...I registers 7 2 Introduction The I O configuration registers control the electrical characteristics of the pins The following characteristics are configurable pin function internal pull up pull down o...

Страница 86: ...ut see Table 150 For any peripheral function the pin direction is controlled automatically depending on the pin s functionality The GPIODIR registers have no effect on peripheral functions 7 3 2 Pin m...

Страница 87: ...for analog to digital conversions This mode is available in those IOCON registers that control pins which can function as ADC inputs If A D mode is selected Hysteresis and Pin mode settings have no ef...

Страница 88: ...guration for pin PIO2_7 0xD0 IOCON_PIO2_8 R W 0x024 I O configuration for pin PIO2_8 0xD0 IOCON_PIO2_1 R W 0x028 I O configuration for pin PIO2_1 DSR SCK1 0xD0 IOCON_PIO0_3 R W 0x02C I O configuration...

Страница 89: ...CT32B0_MAT0 0xD0 IOCON_PIO1_7 R W 0x0A8 I O configuration for pin PIO1_7 TXD CT32B0_MAT1 0xD0 IOCON_PIO3_3 R W 0x0AC I O configuration for pin PIO3_3 RI 0xD0 IOCON_SCK0_LOC R W 0x0B0 SCK0 pin locatio...

Страница 90: ...Table 130 PIO2_4 IOCON_PIO2_4 yes no Table 111 PIO2_5 IOCON_PIO2_5 yes no Table 112 PIO2_6 IOCON_PIO2_6 yes no Table 97 PIO2_7 IOCON_PIO2_7 yes no Table 103 PIO2_8 IOCON_PIO2_8 yes no Table 104 PIO2_9...

Страница 91: ...Reserved Table 97 IOCON_PIO2_6 register IOCON_PIO2_6 address 0x4004 4000 bit description Bit Symbol Value Description Reset value Table 98 IOCON_PIO2_0 register IOCON_PIO2_0 address 0x4004 4008 bit d...

Страница 92: ...bled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9 6 Reserved 0011 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output...

Страница 93: ...ription Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function PIO1_8 0x1 Selects function CT16B1_CAP0 4 3 MODE Selects function mode on chip pull up pull dow...

Страница 94: ...0 0 Standard GPIO output 1 Open drain output 31 11 Reserved Table 102 IOCON_PIO0_2 register IOCON_PIO0_2 address 0x4004 401C bit description Bit Symbol Value Description Reset value Table 103 IOCON_P...

Страница 95: ...abled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9 6 Reserved 0011 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 1 Open drain output 31 11 Reserved Table 105 IOCON_PIO2_1...

Страница 96: ...l down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9 6 Reserved 0011 10 OD Selects pseudo open drain mo...

Страница 97: ...0 default or Standard I O functionality I2CMODE 01 if the pin function is GPIO FUNC 000 00 0x0 Standard mode Fast mode I2C 0x1 Standard I O functionality 0x2 Fast mode Plus I2C 0x3 Reserved 31 10 Rese...

Страница 98: ...x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9 6 Reserved 0011 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 1 Ope...

Страница 99: ...x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9 6 Reserved 0011 10 OD Selects pseudo open drain mode 0 0 Standard GPIO output 1 Ope...

Страница 100: ...function mode on chip pull up pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hyst...

Страница 101: ...her values are reserved 000 0x0 Selects function PIO2_9 4 3 MODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down re...

Страница 102: ...Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function PIO2_2 0x1 Select function DCD 0x2 Select function MISO1 function not available on all part...

Страница 103: ...Reserved Table 119 IOCON_PIO0_8 register IOCON_PIO0_8 address 0x4004 4060 bit description Bit Symbol Value Description Reset value Table 120 IOCON_PIO0_9 register IOCON_PIO0_9 address 0x4004 4064 bit...

Страница 104: ...s function mode on chip pull up pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hys...

Страница 105: ...4 406C bit description Bit Symbol Value Description Reset value Table 123 IOCON_PIO2_11 register IOCON_PIO2_11 address 0x4004 4070 bit description Bit Symbol Value Description Reset value 2 0 FUNC Sel...

Страница 106: ...0_MAT3 4 3 MODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 R...

Страница 107: ...n drain mode 0 0 Standard GPIO output 1 Open drain output 31 11 Reserved Table 125 IOCON_R_PIO1_0 register IOCON_R_PIO1_0 address 0x4004 4078 bit description Bit Symbol Value Description Reset value T...

Страница 108: ...register IOCON_R_PIO1_2 address 0x4004 4080 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function R This functi...

Страница 109: ...istor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9 6 Reserved 0011 10 OD Selects pseudo open drain mode 0 0 Standard GP...

Страница 110: ...function All other values are reserved 000 0x0 Selects function PIO2_3 0x1 Selects function RI 0x2 Selects function MOSI1 function not available on all parts 4 3 MODE Selects function mode on chip pul...

Страница 111: ...0 Standard GPIO output 1 Open drain output 31 11 Reserved Table 131 IOCON_SWDIO_PIO1_3 register IOCON_SWDIO_PIO1_3 address 0x4004 4090 bit description continued Bit Symbol Value Description Reset valu...

Страница 112: ...l Value Description Reset value Table 133 IOCON_PIO1_11 register IOCON_PIO1_11 address 0x4004 4098 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function All other valu...

Страница 113: ...p pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 9...

Страница 114: ...set value 2 0 FUNC Selects pin function All other values are reserved 000 0x0 Selects function PIO1_6 0x1 Selects function RXD 0x2 Selects function CT32B0_MAT0 4 3 MODE Selects function mode on chip p...

Страница 115: ...OCON_PIO1_7 register IOCON_PIO1_7 address 0x4004 40A8 bit description Bit Symbol Value Description Reset value Table 138 IOCON_PIO3_3 register IOCON_PIO3_3 address 0x4004 40AC bit description Bit Symb...

Страница 116: ...d LPC1313 01 parts the modem functions on pins PIO3_1 to PIO3_3 must be configured in the corresponding IOCONFIG registers and also in the IOCON_DSR_LOC IOCON_DCD_LOC and IOCON_RI_LOC registers see Ta...

Страница 117: ...CON_DCD_LOC address 0x4004 40B8 bit description Bit Symbol Value Description Reset value 1 0 DCDLOC Selects pin location for DCD pin this register is only used for parts LPC1311 01 and LPC1313 01 00 0...

Страница 118: ...The LPC1342 43 parts have dedicated USB pins and additional USB functions on some pins UM10375 Chapter 8 LPC13xx Pin configuration Rev 3 14 June 2011 User manual Table 143 LPC13xx pin configuration ov...

Страница 119: ...MAT3 XTALIN PIO2_11 SCK0 XTALOUT PIO1_10 AD6 CT16B1_MAT1 VDD SWCLK PIO0_10 SCK0 CT16B0_MAT2 PIO1_8 CT16B1_CAP0 PIO0_9 MOSI0 CT16B0_MAT1 SWO PIO0_2 SSEL0 CT16B0_CAP0 PIO0_8 MISO0 CT16B0_MAT0 PIO2_7 PIO...

Страница 120: ...DD SWCLK PIO0_10 SCK CT16B0_MAT2 XTALOUT PIO1_10 AD6 CT16B1_MAT1 XTALIN R PIO0_11 AD0 CT32B0_MAT3 PIO0_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE R PIO1_0 AD1 CT32B1_CAP0 RESET PIO0_0 R PIO1_1 AD2 CT32B1_MAT0 P...

Страница 121: ..._11 AD0 CT32B0_MAT3 XTALIN PIO2_11 SCK0 XTALOUT PIO1_10 AD6 CT16B1_MAT1 VDD SWCLK PIO0_10 SCK0 CT16B0_MAT2 PIO1_8 CT16B1_CAP0 PIO0_9 MOSI0 CT16B0_MAT1 SWO PIO0_2 SSEL0 CT16B0_CAP0 PIO0_8 MISO0 CT16B0_...

Страница 122: ...13 LPC1311 13 HVQFN33 package 002aae517 LPC1311FHN33 LPC1311FHN33 01 LPC1313FHN33 LPC1313FHN33 01 Transparent top view PIO0_8 MISO0 CT16B0_MAT0 PIO1_8 CT16B1_CAP0 PIO0_2 SSEL0 CT16B0_CAP0 PIO0_9 MOSI...

Страница 123: ...lave select for SSP0 I CT16B0_CAP0 Capture input 0 for 16 bit timer 0 PIO0_3 USB_VBUS 14 3 yes I O I PU PIO0_3 General purpose digital input output pin LPC1343 only A LOW level on this pin during rese...

Страница 124: ...I CT32B1_CAP0 Capture input 0 for 32 bit timer 1 R PIO1_1 AD2 CT32B1_MAT0 34 5 yes I PU R Reserved Configure for an alternate function in the IOCONFIG block I O PIO1_1 General purpose digital input ou...

Страница 125: ...PIO2_0 General purpose digital input output pin O DTR Data Terminal Ready output for UART I O SSEL1 Slave Select for SSP1 LPC1313FBD48 01 only PIO2_1 DSR SCK1 13 3 yes I O I PU PIO2_1 General purpose...

Страница 126: ...y This pad is not 5 V tolerant 7 When the system oscillator is not used connect XTALIN and XTALOUT as follows XTALIN can be left floating or can be grounded grounding is preferred to reduce susceptibi...

Страница 127: ...O0_3 General purpose digital input output pin LPC1342 43 only A LOW level on this pin during reset starts the ISP command handler a HIGH level starts the USB device enumeration I USB_VBUS Monitors the...

Страница 128: ...er 1 R PIO1_2 AD3 CT32B1_MAT1 24 5 yes I PU R Reserved Configure for an alternate function in the IOCONFIG block I O PIO1_2 General purpose digital input output pin I AD3 A D converter input 3 O CT32B...

Страница 129: ...left floating or can be grounded grounding is preferred to reduce susceptibility to noise XTALOUT should be left floating PIO1_7 TXD CT32B0_MAT1 32 3 yes I O I PU PIO1_7 General purpose digital input...

Страница 130: ...ter 9 LPC13xx General Purpose I O GPIO Rev 3 14 June 2011 User manual Table 146 GPIO configuration Part Package GPIO port 0 GPIO port 1 GPIO port 2 GPIO port 3 Total GPIO pins LPC1311 LPC1311 01 HVQFN...

Страница 131: ...on the pin level A read returns the current state of the pin Table 148 Register overview GPIO base address port 0 0x5000 0000 port 1 0x5001 0000 port 2 0x5002 0000 port 3 0x5003 0000 Name Access Addr...

Страница 132: ...pply when the pins are switched from input to output Pin is configured as input with a HIGH level applied Change pin to output pin drives HIGH level Pin is configured as input with a LOW level applied...

Страница 133: ...ister GPIO0IBE address 0x5000 8008 to GPIO3IBE address 0x5003 8008 bit description Bit Symbol Description Reset value Access 11 0 IBE Selects interrupt on pin x to be triggered on both edges x 0 to 11...

Страница 134: ...ress 0x5003 8014 bit description Bit Symbol Description Reset value Access 11 0 RAWST Raw interrupt status x 0 to 11 0 No interrupt on pin PIOn_x 1 Interrupt requirements met on PIOn_x 0x00 R 31 12 Re...

Страница 135: ...ter at address 0x3FFC sets all masking bits to 1 Write operation If the address bit i 2 associated with the GPIO port bit i i 0 to 11 to be written is HIGH the value of the GPIODATA register bit i is...

Страница 136: ...d protocol The bus supports hot plugging and dynamic configuration of the devices All transactions are initiated by the host controller The host schedules transactions in 1 ms frames Each frame contai...

Страница 137: ...each type of end point FS Full speed LED Light Emitting Diode LS Low Speed MPS Maximum Packet Size NAK Negative Acknowledge PLL Phase Locked Loop RAM Random Access Memory SOF Start Of Frame SIE Serial...

Страница 138: ...and the USB bus The functions of this block include synchronization pattern recognition parallel serial conversion bit stuffing de stuffing CRC checking generation PID verification generation address...

Страница 139: ...ng to establish connection to the USB Re initialization of the USB bus connection can also be performed without having to unplug the cable To use the SoftConnect feature the USB_CONNECT signal should...

Страница 140: ...8 Pin description The device controller can access one USB port 10 9 Clocking and power control This section describes the clocking and power management features of the USB Device Controller 10 9 1 P...

Страница 141: ...uts off the USB_MainClk automatically Once the USB_MainClk is switched off internal registers in the USB clock domain will not be visible to the software When the activity is detected on the bus USB_S...

Страница 142: ...Y should not be disabled while the device is suspended so it can continue to respond to USB bus events 10 9 5 Interrupts The external interrupt generation takes place only if the necessary enable bits...

Страница 143: ...rrupt Enable 0x0000 0000 USBDevIntClr WO 0x08 USB Device Interrupt Clear 0x0000 0000 USBDevIntSet WO 0x0C USB Device Interrupt Set 0x0000 0000 SIE command registers USBCmdCode WO 0x10 USB Command Code...

Страница 144: ...interrupt 1 interrupt pending 8 EP7 USB core interrupt for physical endpoint 7 0 no interrupt 1 interrupt pending 9 DEV_STAT Set when USB Bus reset USB suspend change or Connect change event occurs R...

Страница 145: ...when the corresponding bit in USBDevIntSt is set 0 4 EP3_EN USB core interrupt for physical endpoint 3 0 no interrupt generated 1 interrupt generated when the corresponding bit in USBDevIntSt is set...

Страница 146: ...generated 1 interrupt generated when the corresponding bit in USBDevIntSt is set 0 31 14 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined...

Страница 147: ...eset USB suspend change or Connect change event occurs 0 no effect 1 the corresponding bit in USBDevIntSt is cleared 0 10 CC_EMPTY_CLR The command code register USBCmdCode is empty New command can be...

Страница 148: ...set 0 4 EP3_SET USB core interrupt for physical endpoint 3 0 no effect 1 the corresponding bit in USBDevIntSt is set 0 5 EP4_SET USB core interrupt for physical endpoint 4 0 no effect 1 the correspon...

Страница 149: ...DevIntSt is set 0 13 TXENDPKT_SET The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register USBTxPLen 0 no effect 1 the correspo...

Страница 150: ...dpoint data into this register Before writing to this register the WR_EN bit and LOG_ENDPOINT field of the USBCtrl register should be set appropriately and the packet length should be written to the U...

Страница 151: ...ngth register USBRxPLen address 0x4002 0020 bit description Bit Symbol Value Description Reset value 9 0 PKT_LNGTH The remaining number of bytes to be read from the currently selected endpoint s buffe...

Страница 152: ...ll reset the Write Enable bit If the software resets this bit midway writing will start again from the beginning Both Read Enable and Write Enable bits can be high at the same time for the same logica...

Страница 153: ...ad or write action The USBCmdCode Table 167 and USBCmdData Table 168 registers are used for these accesses A complete access consists of two phases Table 174 USB Device FIQ Select register USBDevFIQSe...

Страница 154: ...le of the Read Current Frame Number command reading 2 bytes USBDevIntClr 0x30 Clear both CCEMPTY CDFULL USBCmdCode 0x00F50500 CMD_CODE 0xF5 CMD_PHASE 0x05 Command while USBDevIntSt 0x10 Wait for CCEMP...

Страница 155: ...d even if the device is not configured in the default state Set Device Status Device FE Write 1 byte Get Device Status Device FE Read 1 byte Get Error Code Device FF Read 1 byte Endpoint Commands Sele...

Страница 156: ...suspend state 1 USB_NEED_CLK is fixed to 1 the 48 MHz clock cannot be stopped when the device enters suspend state 1 INAK_CI Interrupt on NAK for Control IN endpoint 0 0 Only successful transactions g...

Страница 157: ...e number as received by the device 10 11 6 Read Chip ID Command 0xFD Data read 2 bytes The Chip ID is 16 bit wide It returns the value the chip ID LSB first 10 11 7 Set Device Status Command 0xFE Data...

Страница 158: ...ny activity 1 This bit is set to 1 when the device hasn t seen any activity on its upstream port for more than 3 ms 3 SUS_CH Suspend SUS bit change indicator The SUS bit can toggle because The device...

Страница 159: ...eset value 3 0 EC Error Code 0x0 0000 No Error 0001 PID Encoding Error 0010 Unknown PID 0011 Unexpected Packet any packet sequence violation from the specification 0100 Error in Token CRC 0101 Error i...

Страница 160: ...t is cleared by doing a Select Endpoint Clear Interrupt on this endpoint 1 The last received packet for the selected endpoint was a SETUP packet 3 PO Packet over written bit 0 0 The PO bit is cleared...

Страница 161: ...atus of the PO bit after reading Table 184 Set Endpoint Status command description Bit Symbol Value Description Reset value 0 ST Stalled endpoint bit A Stalled control endpoint is automatically unstal...

Страница 162: ...n its corresponding OUT buffer has the Packet Over written PO bit see the Clear Buffer Register set or contains a pending SETUP packet For the control endpoint the validated buffer will be invalidated...

Страница 163: ...ck source is updated 12 Set USB clock divider register see Table 30 to 1 meaning the USB clock is divided by 1 as the input is 48 MHz already 10 12 2 USB device controller initialization 1 Set bits 14...

Страница 164: ...e of the transmit data register Remark USB is a host controlled protocol i e irrespective of whether the data transfer is from the host to the device or from the device to the host the transfer sequen...

Страница 165: ...f INs the status is a single OUT transaction with an empty packet sent by the host Data stage consists of OUTs the status is a single IN transaction for which the device respond with an empty packet S...

Страница 166: ...Software waits for the next endpoint interrupt to occur it already has been generated back in step 6 8 Software responds to the endpoint interrupt by clearing it and begins reading the third packet fr...

Страница 167: ...he interrupt 11 Both B_1 and B_2 are empty and the active buffer is B_2 The next packet written by software will go into B_2 10 14 2 Isochronous endpoints For isochronous endpoints the active data buf...

Страница 168: ...river software are exposed to the user application 1 Clock and pin initialization 2 USB initialization 3 USB connect 4 USB interrupt handler 11 3 1 Clock and pin initialization This function configure...

Страница 169: ...B device type pointer passed in the USB initialization function 11 3 4 USB interrupt handler When the user application is active the interrupt handlers are mapped in the user flash space The user appl...

Страница 170: ...pins rom pUSBD init_clk_pins 4 Set up device type and information USB_DEV_INFO DeviceInfo MSC_DEVICE_INFO MscDevInfo MscDevInfo idVendor USB_VENDOR_ID MscDevInfo idProduct USB_PROD_ID MscDevInfo bcdDe...

Страница 171: ...erface driver The following steps show how to use the USB human interface driver A complete example is available in the LPC13xx code bundle 1 Map the pointer to the on chip driver table ROM rom ROM 0x...

Страница 172: ...BD connect TRUE 11 5 USB driver structure definitions 11 5 1 ROM driver table The following structure is used to access the USB driver table stored in ROM typedefstruct _ROM const USBD pUSBD ROM 11 5...

Страница 173: ...d MSC_Read uint32_t offset uint8_t dst uint32_t length MSC_DEVICE_INFO Table 186 USB device information class structure Member Description DevType USB device class type USB_DEVICE_CLASS_HUMAN_INTERFAC...

Страница 174: ...ion software This function gets called when host sends a write command Input Parameters Offset Destination start address Source Pointer Pointer to the source of data Length Number of bytes to be writt...

Страница 175: ...r to the destination of data Length Number of bytes to be read OutReport OutReport call back function This function is provided by the application software This function gets called when host sends a...

Страница 176: ...ttributes 0xc0 Self Bus power Remote wakeup bMaxPower 0x32 Bus Power required expressed as max mA 2 Mass storage interface descriptor bLength 0x09 Descriptor size in bytes bDescriptorType 0x04 The con...

Страница 177: ...points 0x02 Number of endpoints supported bInterfaceClass 0x03 Class code Human Interface bInterfaceSubClass 0x00 Sublass code None bInterfaceProtocol 0x00 Protocol code None iInterface 0x62 Index of...

Страница 178: ...ype D 0 E 0 M 0 O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Index 0x62 Interface 0 Alternate Setting 0 0x0E USB_STRING_DESCRIPTOR_TYPE bDescriptorType H 0 I 0 D 0 0 0 0 bInterval User Defined Polling interval...

Страница 179: ...r 0x04 USB_STRING_DESCRIPTOR_TYPE 0x0409 Index 0x04 Manufacturer 0x1C USB_STRING_DESCRIPTOR_TYPE N 0 X 0 P 0 0 S 0 e 0 m 0 i 0 c 0 o 0 n 0 d 0 0 Index 0x20 Product 0x28 USB_STRING_DESCRIPTOR_TYPE N 0...

Страница 180: ...responding IOCONFIG registers and also in the IOCON_DSR_LOC IOCON_DCD_LOC and IOCON_RI_LOC registers see Table 140 to Table 101 2 Power In the SYSAHBCLKCTRL register set bit 12 Table 25 3 Peripheral c...

Страница 181: ...clock UART_PCLK is enabled in the UART clock divider register see Table 27 This clock is used by the UART baud rate generator Remark For LPC1311 13 42 43 parts the UART pins must be configured in the...

Страница 182: ...errupt enable bits for the 7 potential UART interrupts When DLAB 0 0x00 U0IIR RO 0x008 Interrupt ID Register Identifies which interrupt s are pending 0x01 U0FCR WO 0x008 FIFO Control Register Controls...

Страница 183: ...ivisor Latch Access Bit DLAB in U0LCR must be zero in order to access the U0THR The U0THR is always Write Only 12 6 3 UART Divisor Latch LSB and MSB Registers U0DLL 0x4000 8000 and U0DLM 0x4000 8004 w...

Страница 184: ...baud rate of the UART 0x00 31 8 Reserved Table 198 UART Interrupt Enable Register U0IER address 0x4000 8004 when DLAB 0 bit description Bit Symbol Value Description Reset value 0 RBRIE Interrupt Enabl...

Страница 185: ...0x4000 8004 when DLAB 0 bit description continued Bit Symbol Value Description Reset value Table 199 UART Interrupt Identification Register U0IIR address 0x4004 8008 Read Only bit description Bit Sym...

Страница 186: ...rrupt U0IIR 3 1 010 shares the second level priority with the CTI interrupt U0IIR 3 1 110 The RDA is activated when the UART Rx FIFO reaches the trigger level defined in U0FCR7 6 and is reset when the...

Страница 187: ...henever THRE 1 and there have not been at least two characters in the U0THR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to U0THR without a THRE in...

Страница 188: ...will clear all bytes in UART Rx FIFO reset the pointer logic This bit is self clearing 2 TXFIFOR TX FIFO Reset 0 0 No impact on either of UART FIFOs 1 Writing a logic 1 to U0FCR 2 will clear all byte...

Страница 189: ...parity 0x3 Forced 0 stick parity 6 BC Break Control 0 0 Disable break transmission 1 Enable break transmission Output pin UART TXD is forced to logic 0 when U0LCR 6 is active high 7 DLAB Divisor Latc...

Страница 190: ...controls the RTS output of the UART If Auto RTS mode is enabled hardware controls the RTS output and the actual value of RTS will be copied in the RTS Control bit of the UART As long as Auto RTS is en...

Страница 191: ...TS mode a change of the CTS signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set Delta CTS bit in the U0MSR will be set though Table 204 lists the conditions for...

Страница 192: ...pin stop Table 205 UART Line Status Register U0LSR address 0x4000 8014 Read Only bit description Bit Symbol Value Description Reset Value 0 RDR Receiver Data Ready U0LSR 0 is set when the U0RBR holds...

Страница 193: ...er goes idle until RXD1 goes to marking state all ones A U0LSR read clears this status bit The time of break detection is dependent on U0FCR 0 Note The break interrupt is associated with the character...

Страница 194: ...o change detected on modem input CTS 1 State change detected on modem input CTS 1 DELTADSR Set upon state change of input DSR Cleared on a U0MSR read 0 0 No change detected on modem input DSR 1 State...

Страница 195: ...us of auto baud pending finished Table 208 Auto baud Control Register U0ACR address 0x4000 8020 bit description Bit Symbol Value Description Reset value 0 START This bit is automatically cleared after...

Страница 196: ...be cleared by setting the corresponding U0ACR ABTOIntClr and ABEOIntEn bits The fractional baud rate generator must be disabled DIVADDVAL 0 during auto baud Also when auto baud is used any write to U0...

Страница 197: ...ate counter is loaded into U0DLM U0DLL and the baud rate will be switched to normal operation After setting the U0DLM U0DLL the end of auto baud interrupt U0IIR ABEOInt will be set if enabled The U0RS...

Страница 198: ...are the standard UART baud rate divider registers and DIVADDVAL and MULVAL are UART fractional baud rate generator specific parameters The value of MULVAL and DIVADDVAL should comply to the following...

Страница 199: ...aud rate calculation UART can operate with or without using the Fractional Divider In real life applications it is likely that the desired baud rate can be achieved using several different Fractional...

Страница 200: ...ter 12 LPC13xx UART Fig 23 Algorithm for setting UART dividers PCLK BR Calculating UART baudrate BR DL est PCLK 16 x BR DLest is an integer DIVADDVAL 0 MULVAL 1 True FR est 1 5 DL est Int PCLK 16 x BR...

Страница 201: ...84 This rate has a relative error of 0 16 from the originally specified 115200 12 6 16 UART Transmit Enable Register U0TER 0x4000 8030 In addition to being equipped with full hardware flow control aut...

Страница 202: ...the transmission of that character is completed but no further characters are sent until this bit is set again In other words a 0 in this bit blocks the transfer of characters from the THR or TX FIFO...

Страница 203: ...the direction control signal on the RTS or DTR pin 0 0 The direction control pin will be driven to logic 0 when the transmitter has data to be sent It will be driven to logic 1 after the last bit of d...

Страница 204: ...generated and the processor can decide whether or not to disable the receiver RS 485 EIA 485 Auto Address Detection AAD mode When both RS485CTRL register bits 0 9 bit mode enable and 2 AAD mode enable...

Страница 205: ...ontrol pin will be driven to logic 0 after the last bit of data has been transmitted 12 7 Architecture The architecture of the UART is shown below in the block diagram The APB interface provides a com...

Страница 206: ...r manual Rev 3 14 June 2011 206 of 368 NXP Semiconductors UM10375 Chapter 12 LPC13xx UART Fig 24 UART block diagram APB INTERFACE U0LCR U0RX DDIS U0LSR U0FCR U0BRG U0TX INTERRUPT PA 2 0 PSEL PSTB PWRI...

Страница 207: ...ing masters without corruption of serial data on the bus Programmable clock allows adjustment of I2C transfer rates Data transfer is bidirectional between masters and slaves Serial clock synchronizati...

Страница 208: ...and the START and STOP conditions A transfer is ended with a STOP condition or with a Repeated START condition Since a Repeated START condition is also the beginning of the next serial transfer the I2...

Страница 209: ...f this register the corresponding bit in the I2C control register is set Writing a zero has no effect on the corresponding bit in the I2C control register 0x00 I2C0STAT RO 0x004 I2C Status Register Du...

Страница 210: ...a buffer register The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits 8 bits of data plus ACK or NACK has been received on...

Страница 211: ...o the STAC bit in the I2CONCLR register When STA is 0 no START condition or Repeated START condition will be generated If STA and STO are both set then a STOP condition is transmitted on the I2C bus i...

Страница 212: ...to defined I2C states When any of these states entered the SI bit will be set For a complete list of status codes refer to tables from Table 235 to Table 238 13 8 3 I2C Data register I2C0DAT 0x4000 0...

Страница 213: ...the frequency of the peripheral I2C clock 4 The values for I2SCLL and I2SCLH must ensure that the data rate is in the appropriate I2C data rate range Each register value must be greater than or equal...

Страница 214: ...ting 0 has no effect I2ENC is the I2C Interface Disable bit Writing a 1 to this bit clears the I2EN bit in the I2CONSET register Writing 0 has no effect 13 8 7 I2C Monitor mode control register I2C0MM...

Страница 215: ...module will enter monitor mode In this mode the SDA output will be forced high This will prevent the I2C module from outputting data of any kind including ACK onto the I2C data bus Depending on the st...

Страница 216: ...egisters are readable and writable and are only used when an I2C interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is the General Call bit When this bit is set...

Страница 217: ...n the I2C block may operate as a master a slave or both In the slave mode the I2C hardware looks for any one of its four slave addresses and the General Call address If one of these addresses is detec...

Страница 218: ...outine which will load the slave address and Write bit to the I2DAT register and then clear the SI bit SI is cleared by writing a 1 to the SIC bit in the I2CONCLR register When the slave address and R...

Страница 219: ...1 to enable the I2C function AA bit must be set to 1 to acknowledge its own slave address or the General Call address The STA STO and SI bits are set to 0 After I2ADR and I2CONSET are initialized the...

Страница 220: ...dress If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is enter...

Страница 221: ...l pad designed to conform to the I2C specification Fig 31 I2C serial interface block diagram APB BUS STATUS REGISTER I2CnSTAT CONTROL REGISTER and SCL DUTY CYLE REGISTERS I2CnCONSET I2CnCONCLR I2CnSCL...

Страница 222: ...slave address with its own slave address 7 most significant bits in I2ADR It also compares the first received 8 bit byte with the General Call address 0x00 If an equality is found the appropriate sta...

Страница 223: ...lock pulse generator provides the SCL clock pulses when the I2C block is in the master transmitter or master receiver mode It is switched off when the I2C block is in a slave mode The I2C output clock...

Страница 224: ...r that correspond to ones in the value written Conversely writing to I2CONCLR will clear bits in the I2C control register that correspond to ones in the value written 13 10 10 Status decoder and statu...

Страница 225: ...m Table 235 to Table 239 13 11 1 Master Transmitter mode In the master transmitter mode a number of data bytes are transmitted to a slave receiver see Figure 34 Before the master transmitter mode can...

Страница 226: ...interrupt service routine to enter the appropriate state service routine that loads I2DAT with the slave address and the data direction bit SLA W The SI bit in I2CON must then be reset before the ser...

Страница 227: ...d data byte or 0 0 0 X Data byte will be transmitted ACK bit will be received No I2DAT action or 1 0 0 X Repeated START will be transmitted No I2DAT action or 0 1 0 X STOP condition will be transmitte...

Страница 228: ...A A other Master continues other Master continues A other Master continues 20H 08H 18H 28H 30H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Data byte Not Acknowledge received after a...

Страница 229: ...t load I2DAT with the 7 bit slave address and the data direction bit SLA R The SI bit in I2CON must then be cleared before the serial transfer can continue When the slave address and the data directio...

Страница 230: ...e bus becomes free 0x40 SLA R has been transmitted ACK has been received No I2DAT action or 0 0 0 0 Data byte will be received NOT ACK bit will be returned No I2DAT action 0 0 0 1 Data byte will be re...

Страница 231: ...A OR A A P other Master continues other Master continues A other Master continues 48H 40H 58H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Acknowledge bit Not Acknowledge received afte...

Страница 232: ...ess followed by the data direction bit which must be 0 W for the I2C block to operate in the slave receiver mode After its own slave address and the W bit have been received the serial interrupt flag...

Страница 233: ...ed No I2DAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned No I2DAT action X 0 0 1 Data byte will be received and ACK will be returned 0x80 Previously addressed with own SLV...

Страница 234: ...s will be recognized if I2ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 0xA0 A STOP condition or Repeated START condition has been received while still addressed as SLV...

Страница 235: ...re Data bytes arbitration lost as Master and addressed as Slave last data byte received is Not acknowledged arbitration lost as Master and addressed as Slave by General Call reception of the own Slave...

Страница 236: ...and a valid status code can be read from I2STAT This status code is used to vector to a state service routine and the appropriate action to be taken for each of these status codes is detailed in Table...

Страница 237: ...been received No I2DAT action or 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address No I2DAT action or 0 0 0 1 Switched to not addressed SLV mode Own SLA wil...

Страница 238: ...when a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge bit...

Страница 239: ...condition see Figure 38 Until this occurs arbitration is not lost by either master since they were both transmitting the same data If the I2C hardware detects a Repeated START condition on the I2C bu...

Страница 240: ...e for an uncontrolled source to cause a bus hang up In such situations the problem may be caused by interference temporary interruption of the bus or a temporary short circuit between SDA and SCL If a...

Страница 241: ...ation so a START should be generated to insure that all I2C peripherals are synchronized 13 11 6 5 Bus error A bus error occurs when a START or STOP condition is detected at an illegal position in the...

Страница 242: ...11 9 I2C interrupt service When the I2C interrupt is entered I2STAT contains a status code which identifies one of the 26 state services to be executed 13 11 10 The state service routines Each state r...

Страница 243: ...uffer 5 Initialize the Master data counter to match the length of the message to be received 6 Exit 13 12 4 I2C interrupt routine Determine the I2C state and which state routine will be used to handle...

Страница 244: ...10 Slave Address Write has been transmitted ACK has been received The first data byte will be transmitted an ACK bit will be received 1 Load I2DAT with first data byte from Master Transmit buffer 2 Wr...

Страница 245: ...to set the STA and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 13 12 7 Master Receive states 13 12 7 1 State 0x40 Previous state was State 08 or State 10 Slave Address Read has been t...

Страница 246: ...rite has been received ACK has been returned Data will be received and ACK returned 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Set up Slave Receive mode...

Страница 247: ...ional data will be read 1 Read data byte from I2DAT into the Slave Receive buffer 2 Decrement the Slave data counter skip to step 5 if not the last data byte 3 Write 0x0C to I2CONCLR to clear the SI f...

Страница 248: ...Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received 1 Load I2DAT from Slave Transmit buffer with first data byte 2 Write 0x04 to I2CONSET to set the...

Страница 249: ...to clear the SI flag 4 Increment Slave Transmit buffer pointer 5 Exit 13 12 9 4 State 0xC0 Data has been transmitted NOT ACK has been received Not addressed Slave mode is entered 1 Write 0x04 to I2CON...

Страница 250: ...t 2 in the PRESETCTRL register Table 9 are set to 1 This de asserts the reset signal to the SSP block 14 3 Features Compatible with Motorola SPI 4 wire TI SSI and National Semiconductor Microwire buse...

Страница 251: ...he active state of this signal can be high or low depending upon the selected bus and mode When the SSP interface is a bus slave this signal qualifies the presence of data from the Master according to...

Страница 252: ...include reserved bits content Table 241 Register overview SSP0 base address 0x4004 0000 Name Access Address offset Description Reset value 1 SSP0CR0 R W 0x000 Control Register 0 Selects the serial cl...

Страница 253: ...tored in used bits only It does not include reserved bits content SSP1CPSR R W 0x010 Clock Prescale Register 0 SSP1IMSC R W 0x014 Interrupt Mask Set and Clear Register 0 SSP1RIS RO 0x018 Raw Interrupt...

Страница 254: ...t transfer 0xA 11 bit transfer 0xB 12 bit transfer 0xC 13 bit transfer 0xD 14 bit transfer 0xE 15 bit transfer 0xF 16 bit transfer 5 4 FRF Frame Format 00 0x0 SPI 0x1 TI 0x2 Microwire 0x3 This combina...

Страница 255: ...O line and receiving SCLK MOSI and SSEL lines 3 SOD Slave Output Disable This bit is relevant only in slave mode MS 1 If it is 1 this blocks this SSP controller from driving the transmit data line MIS...

Страница 256: ...ord masked in the opposite sense from classic computer terminology in which masked meant disabled ARM uses the word masked to mean enabled To avoid confusion we will not use the word masked Table 246...

Страница 257: ...e Time out condition occurs A Receive Time out occurs when the Rx FIFO is not empty and no has not been read for a time out period The time out period is the same for master and slave modes and is det...

Страница 258: ...nterrupt is enabled 0 1 RTMIS This bit is 1 if the Rx FIFO is not empty has not been read for a time out period and this interrupt is enabled The time out period is the same for master and slave modes...

Страница 259: ...bit into their serial shifter on the falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latch...

Страница 260: ...In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the tra...

Страница 261: ...CPHA 1 is shown in Figure 43 which covers both single and continuous transfers In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is...

Страница 262: ...on the rising edges of the SCK signal In the case of a single word transmission after all bits of the data word are transferred the SSEL line is returned to its idle HIGH state one SCK period after th...

Страница 263: ...nsmission lines At the same time the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagated on the falling edges of the SCK signal After all bits have b...

Страница 264: ...forced HIGH The transmit data line SO is arbitrarily forced LOW A transmission is triggered by writing a control byte to the transmit FIFO The falling edge of CS causes the value contained in the bot...

Страница 265: ...control byte of the next frame follows directly after the LSB of the received data from the current frame Each of the received values is transferred from the receive shifter on the falling edge SK af...

Страница 266: ...an input signal transitions A capture event may also optionally generate an interrupt Four 16 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer...

Страница 267: ...15 6 Pin description Table 252 gives a brief summary of each of the counter timer related pins 15 7 Clocking and power control The peripheral clocks PCLK to the 16 bit timers are provided by the syste...

Страница 268: ...is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface 0 TMR16B0MCR R W 0x014 Match Control Register MCR The MCR is used to control if a...

Страница 269: ...e next clock increments the TC and clears the PC 0 TMR16B1PC R W 0x010 Prescale Counter PC The 16 bit PC is a counter which is incremented to the value stored in PR When the value in PR is reached the...

Страница 270: ...cale Counter Table 255 Interrupt Register TMR16B0IR address 0x4000 C000 and TMR16B1IR address 0x4001 0000 bit description Bit Symbol Description Reset value 0 MR0INT Interrupt flag for match channel 0...

Страница 271: ...Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 260 Table 258 Prescale registers...

Страница 272: ...d and TCR 0 will be set to 0 if MR1 matches the TC 0 1 Enabled 0 Disabled 6 MR2I Interrupt on MR2 an interrupt is generated when MR2 matches the value in the TC 0 1 Enabled 0 Disabled 7 MR2R Reset on...

Страница 273: ...a capture event happens on the rising edge of the associated pin the falling edge or on both edges Table 261 Match registers TMR16B0MR0 to 3 addresses 0x4000 C018 to 24 and TMR16B1MR0 to 3 addresses 0...

Страница 274: ...IGH or do nothing Bits EMR 7 6 control the functionality of this output This bit is driven to the CT16B0_MAT1 CT16B1_MAT1 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH 0 2...

Страница 275: ...nsequently duration of the HIGH LOW levels on the same CAP input in this case can not be shorter than 1 2 PCLK 9 8 EMC2 External Match Control 2 Determines the functionality of External Match 2 00 0x0...

Страница 276: ...R16B0CTCR address 0x4000 C070 and TMR16B1CTCR address 0x4001 0070 bit description Bit Symbol Value Description Reset value 1 0 CTM Counter Timer Mode This field selects which rising PCLK edges can inc...

Страница 277: ...the timer reload value 5 If a match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously Note When the match outputs...

Страница 278: ...ws a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer ena...

Страница 279: ...iagram for counter timer0 and counter timer1 is shown in Figure 52 Fig 52 16 bit counter timer block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable CAPTURE...

Страница 280: ...er value when an input signal transitions A capture event may also optionally generate an interrupt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on ma...

Страница 281: ...er related pins 16 7 Clocking and power control The peripheral clocks PCLK to the 32 bit timers are provided by the system clock see Figure 3 These clocks can be disabled through bits 9 and 10 in the...

Страница 282: ...is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface 0 TMR32B0MCR R W 0x014 Match Control Register MCR The MCR is used to control if a...

Страница 283: ...next clock increments the TC and clears the PC 0 TMR32B1PC R W 0x010 Prescale Counter PC The 32 bit PC is a counter which is incremented to the value stored in PR When the value in PR is reached the...

Страница 284: ...the Prescale Counter Table 271 Interrupt Register TMR32B0IR address 0x4001 4000 and TMR32B1IR address 0x4001 8000 bit description Bit Symbol Description Reset value 0 MR0INT Interrupt flag for match...

Страница 285: ...trol what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 276 Table 274 Prescale registers TMR32B0PR address 0x400...

Страница 286: ...the value in the TC 0 1 Enabled 0 Disabled 7 MR2R Reset on MR2 the TC will be reset if MR2 matches it 0 1 Enabled 0 Disabled 8 MR2S Stop on MR2 the TC and PC will be stopped and TCR 0 will be set to...

Страница 287: ...n the falling edge or on both edges 16 8 10 External Match Register TMR32B0EMR and TMR32B1EMR The External Match Register provides both control and status of the external match pins CAP32Bn_MAT 3 0 If...

Страница 288: ...s EMR 9 8 control the functionality of this output This bit is driven to the CT32B0_MAT2 CT16B1_MAT2 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH 0 3 EM3 External Match 3...

Страница 289: ...ssive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input the frequency of the CAP input can not exceed one half of the PCLK clock Consequently duration of the...

Страница 290: ...ddress 0x4001 8070 bit description Bit Symbol Value Description Reset value 1 0 CTM Counter Timer Mode This field selects which rising PCLK edges can increment Timer s Prescale Counter PC or clear PC...

Страница 291: ...ck tick wide positive pulse with a period determined by the PWM cycle length i e the timer reload value 5 If a match register is set to zero then the PWM output will go to HIGH the first time the time...

Страница 292: ...ws a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer ena...

Страница 293: ...for 32 bit counter timer0 and 32 bit counter timer1 is shown in Figure 56 Fig 56 32 bit counter timer block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable C...

Страница 294: ...m the Systick timer clock divider in the system configuration block Table 30 or the system clock see Table 285 17 3 Features 24 bit timer Intended to time intervals of 10 ms Uses dedicated exception v...

Страница 295: ...val The block diagram of the System Tick Timer is shown below in the Figure 57 17 6 Register description 1 Reset Value reflects the data stored in used bits only It does not include content of reserve...

Страница 296: ...nter is enabled When 0 the counter is disabled 0 1 TICKINT System Tick interrupt enable When 1 the System Tick interrupt is enabled When 0 the System Tick interrupt is disabled When enabled the interr...

Страница 297: ...er returns the current value of the System Tick counter Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL 0 31 24 Reserved user software should not write ones to reserve...

Страница 298: ...is intended to be used and there are no rounding errors System clock 72 MHz Program the CTRL register with the value 0x7 which selects the system clock as the clock source and enables the SysTick time...

Страница 299: ...if not periodically reloaded Debug mode Enabled by software but requires a hardware reset or a Watchdog reset interrupt to be disabled Incorrect Incomplete feed sequence causes reset interrupt if ena...

Страница 300: ...caused the reset condition The WDTOF flag must be cleared by software 18 6 Clocking and power control The watchdog timer block uses two clocks PCLK and WDCLK PCLK is used for the APB accesses to the...

Страница 301: ...definitely the intent of the watchdog interrupt is to allow debugging watchdog activity without resetting the device when the watchdog overflows Table 289 Register overview Watchdog timer base address...

Страница 302: ...will ignore feed errors After writing 0xAA to WDFEED access to any Watchdog register other than writing 0x55 to WDFEED causes an immediate reset interrupt when the Watchdog is enabled The reset will...

Страница 303: ...cycles plus 6 PCLK cycles so the value of WDTV is older than the actual value of the timer when it s being read by the CPU 18 8 Block diagram The block diagram of the Watchdog is shown below in the F...

Страница 304: ...urce cannot be changed If the WDT is needed in Deep sleep mode select the watch dog oscillator as the clock source before setting the WDEN bit 19 3 Features Internally resets chip if not reloaded duri...

Страница 305: ...minimum Watchdog interval is TWDCLK 256 4 and the maximum Watchdog interval is TWDCLK 224 4 in multiples of TWDCLK 4 The Watchdog should be used in the following manner Set the Watchdog timer constan...

Страница 306: ...ions the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain When the watchdog timer is counting on WDCLK the synchronization logic will first lock the value of the cou...

Страница 307: ...loads the Watchdog timer with the value contained in WDTC WDTV RO 0x00C Watchdog timer value register This register reads out the current value of the Watchdog timer 0xFF WDWARNINT R W 0x014 Watchdog...

Страница 308: ...terval is TWDCLK 256 4 If the WDPROTECT bit in WDMOD 1 an attempt to change the value of WDTC before the watchdog counter is below the values of WDWARNINT and WDWINDOW will cause a watchdog reset and...

Страница 309: ...s 6 PCLK cycles so the value of WDTV is older than the actual value of the timer when it s being read by the CPU 19 7 5 Watchdog Timer Warning Interrupt register The WDWARNINT register determines the...

Страница 310: ...9 7 7 Watchdog timing examples The following figures illustrate several aspects of Watchdog Timer operation Table 301 Watchdog Timer Warning Interrupt register WDWARNINT 0x4000 4014 bit description Bi...

Страница 311: ...g Timer WWDT Fig 61 Correct Watchdog Feed with Windowed Mode Enabled Correct Feed Event 1201 11FF 1200 WDCLK 4 Watchdog Counter Watchdog Reset 11FC 11FD 2000 1FFE 1FFF 11FE 1FFD 1FFC Conditions WDWIND...

Страница 312: ...ple inputs Optional conversion on transition on input pin or Timer Match signal Individual result registers for each A D channel to reduce interrupt overhead 20 4 Pin description Table 303 gives a bri...

Страница 313: ...of the most recent A D conversion NA 0x008 Reserved AD0INTEN R W 0x00C A D Interrupt Enable Register This register contains enable bits that allow the DONE flag of each A D channel to be included or...

Страница 314: ...select 0 0 Software controlled mode Conversions are software controlled and require 11 clocks 1 Hardware scan mode The AD converter does repeated conversions at the rate selected by the CLKS field sc...

Страница 315: ...n the selected CAP MAT signal 1 Start conversion on a falling edge on the selected CAP MAT signal 31 28 Reserved user software should not write ones to reserved bits The value read from a reserved bit...

Страница 316: ...nd in ADSTAT Table 307 A D Interrupt Enable Register AD0INTEN address 0x4001 C00C bit description Bit Symbol Description Reset Value 7 0 ADINTEN These bits allow control over which A D channels genera...

Страница 317: ...er are one Software can use the Interrupt Enable bit in the interrupt controller that corresponds to the ADC to control whether this results in an interrupt The result register for an A D channel that...

Страница 318: ...emory by the application program in a running system The bootloader version can be read by ISP IAP calls see Section 21 13 12 or Section 21 14 6 and is part of the chip marking for some LPC13xx parts...

Страница 319: ...rogramming In Application IAP programming is performing erase and write operation on the on chip flash memory as directed by the end user application code The LPC134x supports ISP from the USB port th...

Страница 320: ...he memory region starting from the address 0x0000 0000 21 6 Flash content protection mechanism The LPC13xx is equipped with the Error Correction Code ECC capable Flash memory The purpose of an error c...

Страница 321: ...hould respond by sending the crystal frequency in kHz at which the part is running For example if the part is running at 10 MHz the response from the host should be 10000 CR LF OK CR LF string is sent...

Страница 322: ...the ASCII control character DC1 start The host should also support the same flow control scheme 21 8 5 ISP command abort Commands can be aborted by sending the ASCII control character ESC This featur...

Страница 323: ...eprogrammed If CRP1 or CRP2 is enabled the user flash is erased when the file is deleted If CRP1 is enabled or no CRP is selected the user flash is erased and reprogrammed when the new file is copied...

Страница 324: ...14 8 2 For details on available ISP commands based on the CRP settings see Section 21 12 Fig 63 Boot process flowchart RESET INITIALIZE RECEIVE CRYSTAL FREQUENCY RUN ISP COMMAND HANDLER RUN AUTO BAUD...

Страница 325: ...urity in the system so that access to the on chip flash and use of the ISP can be restricted When needed CRP is invoked by programming a specific pattern in flash location at 0x0000 02FC IAP commands...

Страница 326: ...sed Since compare command is disabled in case of partial updates the secondary loader should implement checksum mechanism to verify the integrity of the flash CRP2 0x87654321 Access to chip via the SW...

Страница 327: ...is allowed in NO_ISP mode but disabled in CRP3 mode The NO_ISP mode does not offer any code protection CRP2 Yes High No No NA CRP2 Yes Low No Yes No CRP3 Yes x No No NA CRP1 No x No Yes Yes CRP2 No x...

Страница 328: ...Table 317 ISP command summary ISP Command Usage Described in Unlock U Unlock Code Table 318 Set Baud Rate B Baud Rate stop bit Table 319 Echo A setting Table 320 Write to RAM W start address number o...

Страница 329: ...actual number of bytes sent The ISP command handler compares it with the check sum of the received bytes If the check sum matches the ISP command handler responds with OK CR LF to continue further tra...

Страница 330: ...his command makes flash write erase operation a two step process Table 321 ISP Write to RAM command Command W Input Start Address RAM address where data bytes are to be written This address should be...

Страница 331: ...emories an erase should be performed after following 16 consecutive writes inside the same page Note that the erase operation then erases the entire sector Remark Once a page has been written to 16 ti...

Страница 332: ...ram the flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again once the copy command is successfully executed...

Страница 333: ...e erased using this command This command only allows erasure of all user sectors when the code read protection is enabled Example E 2 3 CR LF erases the flash sectors 2 and 3 Table 327 ISP Blank check...

Страница 334: ...oot code version number in ASCII format It is to be interpreted as byte1 Major byte0 Minor Description This command is used to read the boot code version number Table 331 ISP Compare command Command M...

Страница 335: ...Source address is not mapped in the memory map Count value is taken in to consideration where applicable 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map Count value is taken...

Страница 336: ...FFF 1FF0 location and it is thumb code The IAP function could be called in the following way using C Define the IAP location entry point Since the 0th bit of the IAP location is set there will be a ch...

Страница 337: ...p RAM for execution The user program should not be use this space if IAP flash programming is permitted in the application 21 14 1 Prepare sector s for write operation This command makes flash write e...

Страница 338: ...gle sector use the same Start and End sector numbers Table 336 IAP Copy RAM to flash command Command Copy RAM to flash Input Command code 51 decimal Param0 DST Destination flash address where data byt...

Страница 339: ...can not be erased by this command To erase a single sector use the same Start and End sector numbers Table 338 IAP Blank check sector s command Command Blank check sector s Input Command code 53 deci...

Страница 340: ...ndary Param1 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param2 Number of bytes to be compared should be a multiple of 4 Return Code CMD_SUCCE...

Страница 341: ...Result0 The first 32 bit word at the lowest address Result1 The second 32 bit word Result2 The third 32 bit word Result3 The fourth 32 bit word Description This command is used to read the unique ID T...

Страница 342: ...per setting of this register may result in incorrect operation of the LPC13xx flash memory Table 345 Memory mapping in debug mode Memory mapping mode Memory start address visible at 0x0000 0004 Bootlo...

Страница 343: ...Bit Symbol Value Description Reset value 1 0 FLASHTIM Flash memory access time FLASHTIM 1 is equal to the number of system clocks used for flash access 10 0x0 1 system clock flash access time for syst...

Страница 344: ...cleared via the FMSTATCLR register before starting a signature generation operation otherwise the status might indicate completion of a previous operation Table 350 FMSW0 register bit description FMS...

Страница 345: ...eration A signature can be generated for any part of the flash contents The address range to be used for signature generation is defined by writing the start address to the FMSSTART register and the s...

Страница 346: ...bit signature can be read from the FMSW0 to FMSW3 registers The 128 bit signature reflects the corrected data read from the flash The 128 bit signature reflects flash parity bits and check bit values...

Страница 347: ...cell allows additional software controlled trace 22 3 Introduction Debug and trace functions are integrated into the ARM Cortex M3 Serial wire debug and trace functions are supported The ARM Cortex M3...

Страница 348: ...e System Tick Timer is automatically stopped whenever the CPU is stopped Other peripherals are not affected Remark Note that the debug mode is not supported in any of the reduced power modes 22 6 2 De...

Страница 349: ...1 349 of 368 NXP Semiconductors UM10375 Chapter 22 LPC13xx Serial Wire Debug SWD The VTREF pin on the SWD connector enables the debug connector to match the target voltage Fig 66 Connecting the SWD pi...

Страница 350: ...formance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BOD BrownOut Detection DCC Debug Communication Channel DSP Digital Signal Processing EOP End Of Packet ETM Embed...

Страница 351: ...suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to...

Страница 352: ...x4004 8078 bit description 25 Table 25 System AHB clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description 25 Table 26 SSP0 clock divider register SSP0CLKDIV address 0x4004 8094 bit de...

Страница 353: ...Table 78 Interrupt Priority Register 0 IPR0 address 0xE000 E400 bit description 77 Table 79 Interrupt Priority Register 1 IPR1 address 0xE000 E404 bit description 77 Table 80 Interrupt Priority Regis...

Страница 354: ...ddress 0x4004 4098 bit description 112 Table 134 IOCON_PIO3_2 register IOCON_PIO3_2 address 0x4004 409C bit description 113 Table 135 IOCON_PIO1_5 register IOCON_PIO1_5 address 0x4004 40A0 bit descrip...

Страница 355: ...ors 176 Table 191 HID descriptors 177 Table 192 UART pin description 180 Table 193 Register overview UART base address 0x4000 8000 182 Table 194 UART Receiver Buffer Register U0RBR address 0x4000 8000...

Страница 356: ...atus register SSP0RIS address 0x4004 0018 SSP1RIS address 0x4005 8018 bit description 257 Table 250 SSP Masked Interrupt Status register SSP0MIS address 0x4004 001C SSP1MIS address 0x4005 801C bit des...

Страница 357: ...address 0x4000 000C bit description 303 Table 295 Register overview Watchdog timer base address 0x4000 4000 307 Table 296 Watchdog Mode register WDMOD 0x4000 4000 bit description 307 Table 297 Watchdo...

Страница 358: ...ster FLASHCFG address 0x4003 C010 bit description 343 Table 348 Flash Module Signature Start register FMSSTART 0x4003 C020 bit description 343 Table 349 Flash Module Signature Stop register FMSSTOP 0x...

Страница 359: ...mat and states in the Slave Transmitter mode 238 Fig 38 Simultaneous Repeated START conditions from two masters 240 Fig 39 Forced access to a busy I2C bus 240 Fig 40 Recovering from a bus obstruction...

Страница 360: ...ivider register 27 3 5 21 SSP1 clock divider register 28 3 5 22 Trace clock divider register 28 3 5 23 SYSTICK clock divider register 28 3 5 24 USB clock source select register 28 3 5 25 USB clock sou...

Страница 361: ...xpected value 58 5 6 Power routine 59 5 6 1 set_power 59 5 6 1 1 Param0 main clock 60 5 6 1 2 Param1 mode 60 5 6 1 3 Param2 system clock 60 5 6 1 4 Code examples 61 5 6 1 4 1 Invalid frequency device...

Страница 362: ...116 7 4 45 IOCON_DCD_LOC 116 7 4 46 IOCON_RI_LOC 117 Chapter 8 LPC13xx Pin configuration 8 1 How to read this chapter 118 8 2 LPC134x pin configuration 119 8 3 LPC131x pin configuration 121 8 4 Pin de...

Страница 363: ...Data read 1 byte 158 10 11 9 Get Error Code Command 0xFF Data read 1 byte 159 10 11 10 Select Endpoint Command 0x00 0x09 Data read 1 byte optional 159 10 11 11 Select Endpoint Clear Interrupt Command...

Страница 364: ...5 Auto Address Detection AAD mode 204 RS 485 EIA 485 Auto Direction Control 204 RS485 EIA 485 driver delay time 205 RS485 EIA 485 output inversion 205 12 7 Architecture 205 Chapter 13 LPC13xx I2C bus...

Страница 365: ...13 12 8 7 State 0x90 247 13 12 8 8 State 0x98 248 13 12 8 9 State 0xA0 248 13 12 9 Slave Transmitter states 248 13 12 9 1 State 0xA8 248 13 12 9 2 State 0xB0 248 13 12 9 3 State 0xB8 248 13 12 9 4 St...

Страница 366: ...4 16 8 4 Prescale Register TMR32B0PR address 0x4001 400C and TMR32B1PR address 0x4001 800C 284 16 8 5 Prescale Counter Register TMR32B0PC address 0x4001 4010 and TMR32B1PC address 0x4001 8010 285 16 8...

Страница 367: ...1 Hardware triggered conversion 317 20 7 2 Interrupts 317 Chapter 21 LPC13xx Flash memory programming firmware 21 1 How to read this chapter 318 21 2 Bootloader 318 21 2 1 Bootloader code version 5 2...

Страница 368: ...21 15 2 Serial Wire Debug SWD flash programming interface 342 21 16 Register description 342 21 16 1 Flash configuration register 342 21 16 2 Signature generation address and control registers 343 21...

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