
UM10375
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
User manual
Rev. 3 — 14 June 2011
303 of 368
NXP Semiconductors
UM10375
Chapter 18: LPC13xx WatchDog Timer (WDT)
18.7.4 Watchdog Timer Value register (WDTV - 0x4000 400C)
The WDTV register is used to read the current value of Watchdog timer.
When reading the value of the 24-bit timer, the lock and synchronization procedure takes
up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual
value of the timer when it's being read by the CPU.
18.8 Block diagram
The block diagram of the Watchdog is shown below in the
. The synchronization
logic (PCLK - WDCLK) is not shown in the block diagram.
Table 294. Watchdog Timer Value register (WDTV - address 0x4000 000C) bit description
Bit
Symbol
Description
Reset Value
23:0
COUNT
Counter timer value.
0x0000 00FF
31:24
-
Reserved
-
Fig 58. Watchdog block diagram
WDTC
24-BIT DOWN COUNTER
WDINT
WDTOF WDRESET
WDEN
SHADOW BIT
reset
interrupt
4
WDFEED
feed ok
feed error
wdt_clk
underflow
enable
count
WMOD register
feed sequence