NXP Semiconductors LPC1311, Руководство пользователя, Страница: 50 / 368

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User manual Rev. 3 — 14 June 2011 50 of 368
NXP Semiconductors
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Chapter 3: LPC13xx System configuration
3.11.4.1 Normal mode
In this mode the post divider is enabled, giving a 50% duty cycle clock with the following
frequency relations:
(1)
To select the appropriate values for M and P, it is recommended to follow these steps:
1. Specify the input clock frequency Fclkin.
2. Calculate M to obtain the desired output frequency FCLKOUT with
M = FCLKOUT / FCLKIN.
3. Find a value so that FCCO = 2

P

FCLKOUT.
4. Verify that all frequencies and divider values conform to the limits specified in Table 10
and Table 12 .
5. Ensure that FCLKOUT < 100 MHz.
Table 58 shows how to configure the PLL for a 12 MHz crystal oscillator using the
SYSPLLCTRL or USBPLLCTRL registers ( Table 10 or Table 11 ). The main clock is
equivalent to the system clock if the system clock divider SYSAHBCLKDIV is set to one
(see
Table 24 ).
3.11.4.2 Power-down mode
In this mode, the internal current reference will be turned off, the oscillator and the
phase-frequency detector will be stopped and the dividers will enter a reset state. While in
Power-down mode, the lock output will be low, to indicate that the PLL is not in lock. When
FCLKOUT Frequency of sys_pllclkout;
< 100 MHz Frequency of usb_pllclkout;
< 100 MHz
P System PLL post divider ratio; PSEL
bits in SYSPLLCTRL (see
Section 3.5.3 ).
USB PLL post divider ratio; PSEL bits
in USBPLLCTRL (see
Section 3.5.5 ).
M System PLL feedback divider register;
MSEL bits in SYSPLLCTRL (see
Section 3.5.3 ).
USB PLL feedback divider register;
MSEL bits in USBPLLCTRL (see
Section 3.5.5 ).
Table 57. PLL frequency parameters
Parameter System PLL USB PLL
Table 58. PLL configuration examples
PLL input
clock
sys_pllclkin
(FCLKIN) Main clock
(FCLKOUT) MSEL bits
Table 10
(binary)
M divider
value PSEL bits
Table 10
(binary)
P divider
value FCCO
frequency
12 MHz 72 MHz 00101 6 01 2 288 MHz
12 MHz 48 MHz 00011 4 01 2 192 MHz
12 MHz 36 MHz 00010 3 10 4 288 MHz
12 MHz 24 MHz 00001 2 10 4 192 MHz
FCLKOUT M FCLKIN

FCCO
 
2 P
   
= =