NXP Semiconductors LPC11U1x, Руководство пользователя

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User manual Rev. 5.5 — 21 December 2016 496 of 523
NXP Semiconductors
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Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.5.3.8 SCB usage hints and tips
Ensure software uses aligned 32-bit word size transactions to access all the SCB
registers.
24.5.4 System timer, SysTick
When enabled, the timer counts down from the reload value to zero, reloads (wraps to)
the value in the SYST_RVR on the next clock cycle, then decrements on subsequent
clock cycles. Writing a value of zero to the SYST_RVR disables the counter on the next
wrap. When the counter transitions to zero, the COUNTFLAG status bit is set to 1.
Reading SYST_CSR clears the COUNTFLAG bit to 0.
Writing to the SYST_CVR clears the register and the COUNTFLAG status bit to 0. The
write does not trigger the SysTick exception logic. Reading the register returns its value at
the time it is accessed.
Remark: When the processor is halted for debugging the counter does not decrement.
The system timer registers are:
[1] SysTick calibration value.
24.5.4.1 SysTick Control and Status Register
The SYST_CSR enables the SysTick features. See the register summary in for its
attributes. The bit assignments are:
Table 450. SHPR3 register bit assignments
Bits Name Function
[31:24] PRI_15 Priority of system handler 15, SysTick exception
[23:16] PRI_14 Priority of system handler 14, PendSV
[15:0] - Reserved
Table 451. System timer registers summary
Address Name Type Reset
value Description
0xE000E010 SYST_CSR RW 0x00000000 Section 24.5.4.1
0xE000E014 SYST_RVR RW Unknown Section 24–24.5.4.2
0xE000E018 SYST_CVR RW Unknown Section 24–24.5.4.3
0xE000E01C SYST_CALIB RO 0xC0000000
[1]
Section 24–24.5.4.4
Table 452. SYST_CSR bit assignments
Bits Name Function
[31:17] - Reserved.
[16] COUNTFLAG Returns 1 if timer counted to 0 since the last read of this register.
[15:3] - Reserved.