UM10462
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User manual
Rev. 5.5 — 21 December 2016
483 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.4.7.9.3
Restrictions
There are no restrictions.
24.4.7.9.4
Condition flags
This instruction does not change the flags.
24.4.7.9.5
Examples
SEV ; Send Event
24.4.7.10 SVC
Supervisor Call.
24.4.7.10.1
Syntax
SVC #
imm
where:
imm
is an integer in the range 0-255.
24.4.7.10.2
Operation
The SVC instruction causes the SVC exception.
imm
is ignored by the processor. If required, it can be retrieved by the exception handler to
determine what service is being requested.
24.4.7.10.3
Restrictions
There are no restrictions.
24.4.7.10.4
Condition flags
This instruction does not change the flags.
24.4.7.10.5
Examples
SVC #0x32 ; Supervisor Call (SVC handler can extract the immediate value
; by locating it via the stacked PC)
24.4.7.11 WFE
Wait For Event.
Remark:
The WFE instruction is not implemented on the LPC11U3x/2x/1x.
24.4.7.11.1
Syntax
WFE
24.4.7.11.2
Operation
If the event register is 0, WFE suspends execution until one of the following events
occurs: