APPENDIX D LIST OF CAUTIONS
User’s Manual U18172EJ2V0UD
311
(4/15)
Chapter
Cl
assi
fi
cati
on
Function Details
of
Function
Cautions Page
The timer operation must be stopped before setting CRC00.
pp. 88,
116
Soft
When the clear & start mode entered on a match between TM00 and CR000 is
selected by 16-bit timer mode control register 00 (TMC00), CR000 should not be
specified as a capture register.
pp. 88,
115
Hard
CRC00:
Capture/
compare control
register 00
To ensure the reliability of the capture operation, the capture trigger requires a
pulse longer than two cycles of the count clock selected by prescaler mode
register 00 (PRM00) (refer to Figure 6-18).
pp. 88,
118
Timer operation must be stopped before setting other than OSPT00.
pp. 89,
116
If LVS00 and LVR00 are read, 0 is read.
pp. 89,
116
OSPT00 is automatically cleared after data is set, so 0 is read.
pp. 89,
116
Soft
Do not set OSPT00 to 1 other than in one-shot pulse output mode.
pp. 89,
116
Hard
A write interval of two cycles or more of the count clock selected by prescaler
mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively.
pp. 89,
116
Soft
TOC00: 16-bit
timer output
control register
00
When the TOE00 is 0, set the TOE00, LVS00, and LVR00 at the same time with
the 8-bit memory manipulation instruction. When the TOE00 is 1, the LVS00 and
LVR00 can be set with the 1-bit memory manipulation instruction.
p. 90
Always set data to PRM00 after stopping the timer operation.
pp. 90,
116
Soft
If the valid edge of the TI000 pin is to be set as the count clock, do not set the
clear/start mode and the capture trigger at the valid edge of the TI000 pin.
pp. 90,
118
In the following cases, note with caution that the valid edge of the TI0n0 pin is
detected.
<1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the
operation of the 16-bit timer counter 00 (TM00) is enabled
→
If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00
operation is enabled.
<2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00
operation is then enabled after a low level is input to the TI0n0 pin
→
If the falling edge or both rising and falling edges are specified as the valid
edge of the TI0n0 pin, a falling edge is detected immediately after the TM00
operation is enabled.
<3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00
operation is then enabled after a high level is input to the TI0n0 pin
→
If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00
operation is enabled.
pp. 91,
120
Chapter 6
Hard
16-bit
timer/
event
counters
00
PRM00:
Prescaler mode
register 00
The sampling clock used to eliminate noise differs when a TI000 valid edge is
used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is f
XP
, and in the latter case the count clock is selected by
prescaler mode register 00 (PRM00). The capture operation is not performed
until the valid edge is sampled and the valid level is detected twice, thus
eliminating noise with a short pulse width.
pp. 91,
120
