APPENDIX D LIST OF CAUTIONS
User’s Manual U18172EJ2V0UD
318
(11/15)
Chapter
Cl
assi
fi
cati
on
Function Details
of
Function
Cautions Page
For an external reset, input a low level for 2
µ
s or more to the RESET pin.
p. 187
During reset signal generation, the system clock and low-speed internal oscillation
clock stop oscillating.
p. 187
When the RESET pin is used as an input-only port pin (P34), the 78K0S/KU1+ is
reset if a low level is input to the RESET pin after reset is released by the POC
circuit, the LVI circuit and the watchdog timer and before the option byte is
referenced again. The reset status is retained until a high level is input to the
RESET pin.
p. 187
−
The LVI circuit is not reset by the internal reset signal of the LVI circuit.
p. 188
Timing of reset
by overflow of
watchdog timer
The watchdog timer is also reset in the case of an internal reset of the watchdog
timer.
p. 190
Chapter 12
Hard
Reset
function
RESF: Reset
control flag
register
Do not read data by a 1-bit memory manipulation instruction.
p. 194
Soft
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
p. 195
Hard
Functions of
power-on-clear
circuit
Because the detection voltage (V
POC
) of the POC circuit is in a range of 2.1 V
±
0.1
V, use a voltage in the range of 2.2 to 5.5 V.
p. 195
Chapter 13
Soft
Power-
on-clear
circuit
Cautions for
power-on-clear
circuit
In a system where the supply voltage (V
DD
) fluctuates for a certain period in the
vicinity of the POC detection voltage (V
POC
), the system may be repeatedly reset
and released from the reset status. In this case, the time from release of reset to
the start of the operation of the microcontroller can be arbitrarily set by taking the
following action.
p. 197
To stop LVI, follow either of the procedures below.
•
When using 8-bit manipulation instruction: Write 00H to LVIM.
•
When using 1-bit memory manipulation instruction: Clear LVION to 0.
p. 200
LVIM: Low-
voltage detect
register
Be sure to set bits 2 to 6 to 0.
p. 200
Bits 4 to 7 must be set to 0.
p. 201
LVIS: Low-
voltage
detection level
select register
If a value other than the above is written during LVI operation, the value becomes
undefined at the very moment it is written, and thus be sure to stop LVI (bit
7(LVION) = 0 on the LVIM register) before writing.
p. 201
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <3>.
p. 202
When used as
reset
If supply voltage (V
DD
)
≥
detection voltage (V
LVI
) when LVIM is set to 1, an internal
reset signal is not generated.
p. 202
Chapter 14
Soft
Low-
voltage
detector
Cautions for
low-voltage
detector
In a system where the supply voltage (V
DD
) fluctuates for a certain period in the
vicinity of the LVI detection voltage (V
LVI
), the operation is as follows depending
on how the low-voltage detector is used.
<1> When used as reset
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operation of the
microcontroller can be arbitrarily set by taking action (1) below.
<2> When used as interrupt
Interrupt requests may be frequently generated. Take (b) of action (2) below.
p. 206
