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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U18172EJ2V0UD
31
Figure 3-5. Data Memory Addressing (
µ
PD78F9201)
Special function registers (SFR)
256
×
8 bits
Internal high-speed RAM
128
×
8 bits
Flash memory
2,048
×
8 bits
Use prohibted
Direct addressing
Register indirect addressing
Based addressing
SFR addressing
Short direct addressing
F F F F H
F F 0 0 H
F E F F H
F F 2 0 H
F E 1 F H
F E 8 0 H
F E 7 F H
0 8 0 0 H
0 7 F F H
0 0 0 0 H