Theory of Operation
Chapter 6
GPIB-1014 User Manual
6-4
© National Instruments Corporation
address. If DS* from the master is also asserted, local signal BRDEN* is asserted. Further
decoding is necessary to determine which register is being addressed. Eight data lines (A8
through A1) are latched by an AS573 8-bit register at the start of every slave cycle (that is, when
AS* is low and DTACK* from the last cycle is high) to provide the address decoder with
constant address information.
When the GPIB-1014 has been addressed (signal BRDEN* is active) and VMEbus address line
A8 is a logic zero, the DMAC select signal DMACS* is driven active, indicating that the DMAC
has been addressed. Address lines A7 through A1, DS0* and DS1*, are then used to select one
of the internal registers of the DMAC. The DMAC can function as an 8- or 16-bit slave. All
registers within the chip can be accessed with 8- or 16-bit transfers. A 16-bit access to an 8-bit
register will return arbitrary data in the unused bits. Reading from unused locations within the
address range occupied by the DMAC results in a normal bus cycle but returns all ones. Also,
DMAC asserts the DTACK* to prevent a bus error. A write to an unused location results in a
normal bus cycle but no write occurs. Like a read, DMAC asserts DTACK* to prevent a bus
error.
When the GPIB-1014 has been addressed, VMEbus address line A8 is a logic 1, A4 is a logic 1,
the lower data strobe DS0* is active, and the TLC select signal TLCCS* is driven active,
indicating that the TLC has been addressed. Address lines A3 through A1 are used to select the
internal registers of the TLC. These lines are gated with the onboard signal CCBYTE and are
connected to the TLC register select lines RS2 through RS0. The TLC functions as an 8-bit
slave. It transfers data on the lower eight bits of the VMEbus data bus. The TLC registers are
located at consecutive odd addresses and respond only when DS0* is asserted. The TLC
responds to 16-bit transfers, but the upper data byte is not used during an I/O write and returns all
ones during an I/O read. As described in the DMA Gating and Control section, signal CCBYTE
forces a write cycle to the Auxiliary Mode Register inside the TLC when it is asserted.
When the GPIB-1014 has been addressed, VMEbus address line A8 is a logic 1, A4 is a logic 0,
A2 is a logic 0, and Configuration Register 1 is addressed. When A8 is a logic 1, A4 is a logic 0,
A2 is a logic 1, and Configuration Register 2 is addressed. These 8-bit registers respond only to
I/O write operations (write-only) and are loaded via the lower eight data lines. They can be
accessed with an 8- or 16-bit I/O write operation. A read from either of these registers results in
a normal bus cycle, but returns all ones. In addition, a pair of F74 flip-flops is used to keep local
signal BRDEN* asserted until both Data Strobes (DS0* and DS1*) and Address Strobe (AS*)
from the VMEbus master have gone away and the board has released DTACK* to end the
current slave read/write cycle.
Accesses to locations within the 512-byte block that do not specifically address either the
DMAC, the TLC, or one of the Configuration Registers result in a bus error because the
GPIB-1014 does not respond.
Clock and Reset Circuitry
The clock and reset circuitry on the GPIB-1014 is used to generate the onboard clock and reset
signals. The VMEbus signal SYSCLK (16 MHz) is received with a 74LS240 receiver and is
divided by a 74LS74A flip-flop to generate the onboard 8-MHz clock signal (CLK). This clock
is used by the TLC and the DMAC. The 16-MHz clock is used by the Timing State Machine to
