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Chapter 5

Programming Considerations

© National Instruments Corporation

5-15

GPIB-1014 User Manual

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For array or linked chaining, load the MFCR of Channel 0 with the proper data to
generate the required Address Modifier Code to access the data blocks. See Tables
3-1 and 3-2 for recommended values.

•

Set up the data blocks and the address & transfer count array in VMEbus memory.
The total number of bytes in the data block should be n-1 bytes. Figures 6-1 and 6-2
describe how to set up the array for both chaining modes.

h. Finally, interrupts are generally not enabled in Channel 0. The CPR, NIVR, DAR,

DFCR, and EIVR of Channel 0 are generally not used.

3. Channel 1 is used to control the interrupts from the board and to implement the carry cycle

feature. A carry cycle array is constructed in memory. Chaining is used to transfer the array.
The carry cycle array is just an address & transfer count array (that is, an array of pointers
that point to the data blocks to be transferred). The procedure for configuring Channel 1 is as
follows:

a. Write to the CCR of Channel 1 with the SAB bit set to abort the channel operation in case

it is still active.

b. Write 0xFF (hex) to the CSR of Channel 1 to clear any leftover error or status bits.

c. Load the DCR of Channel 1 with the proper value to select the DMA transfer mode, cycle

steal without hold, or cycle steal with hold. Set the DTYP bits to 10 (device with ACK*,
implicitly addressed); set the DPS bit to 0 (8-bit port size); and set the PCL bits to 00
(status input) or 01 (status input with interrupt). If the cycle steal with hold transfer mode
is selected, write to the GCR to select the required timeout. (See the GCR description in
Chapter 4 for recommended values.

d. Write to the OCR of Channel 1. Set the DIR bit to reflect the direction of transfer

(0=Memory-to-GPIB, 1=GPIB-to-Memory), set the SIZE bits to 00 (byte), set the
CHAIN bits to 10 or 11 (array or linked chaining), and set the REQG bits to 10 (REQ*
line initiates transfer). The array chaining feature is usually used to implement the carry
cycle because of its simplicity.

e. Set the SCR of Channel 1 to 00 (addresses do not count).

f.

For array or linked chaining, load the BFCR of Channel 1 with the proper value to
generate the required address modifier code, which then accesses the address & transfer
count array. (See Tables 3-1 and 3-2 for recommended values.)

g. For array or linked chaining, load Channel 1 BAR with the beginning address of the

address & transfer count array.

h. For array chaining, load the BTCR of Channel 1 with 2 (two entries in the carry cycle

array). Linked chaining does not use the BTCR.

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Содержание GPIB-1014 Series

Страница 1: ...Copyright 1985 1997 National Instruments Corporation All Rights Reserved GPIB 1014 User Manual March 1997 Edition Part Number 3 70945A 01...

Страница 2: ...90 0 Belgium 02 757 00 20 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 57348...

Страница 3: ...liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFI...

Страница 4: ...or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel an...

Страница 5: ...ference from the equipment to radio reception in commercial areas Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to c...

Страница 6: ...aster Direct Memory Access 2 5 Interrupter 2 6 Data Transfer Bus DTB Requester 2 7 VMEbus Modules Not Provided 2 7 Diagnostic Aids 2 7 Data Transfer Features 2 7 Programmed I O Transfers 2 8 GPIB 1014...

Страница 7: ...liary Register B AUXRB 4 39 Auxiliary Register E AUXRE 4 41 Address Register 0 ADR0 4 42 Address Register ADR 4 43 Address Register 1 ADR1 4 44 End of String Register EOSR 4 45 DMA Registers 4 46 Addr...

Страница 8: ...n END or EOS 5 19 Using Programmed I O 5 19 Sending and Receiving Data 5 19 Sending END or EOS 5 20 Terminating on END or EOS 5 20 Interrupts 5 20 Serial Polls 5 22 Conducting a Serial Poll 5 22 Respo...

Страница 9: ...ple Block Operations 6 19 Continued Operations 6 19 Array Chaining Operations 6 19 Linked Chaining Operations 6 20 Error Conditions 6 21 GPIB Interface 6 23 Test and Troubleshooting 6 24 DMA Stand Alo...

Страница 10: ...gure 1 1 GPIB 1014 Interface Board 1 2 Figure 2 1 GPIB 1014 with a VMEbus Computer 2 9 Figure 2 2 GPIB 1014 in a Multiprocessor Application 2 10 Figure 2 3 GPIB 1014 Block Diagram 2 11 Figure 3 1 Part...

Страница 11: ...ble 3 1 Programming Values for Default Settings of W3 W4 and W5 3 6 Table 3 2 Setting the Address Modifier Code Bits AM5 AM0 3 6 Table 3 3 GPIB 1014 Pin Assignment on VMEbus Connector P1 3 8 Table 3 4...

Страница 12: ...al parallel poll process Chapter 6 Theory of Operation contains a functional overview of the GPIB 1014 board and explains the operation of each functional block making up the GPIB 1014 Chapter 7 Diagn...

Страница 13: ...ng conventions are used to distinguish elements of text throughout this manual italic Italic text denotes emphasis a cross reference or an introduction to a key concept IEEE 488 IEEE 488 is used throu...

Страница 14: ...ry Access Controller Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we w...

Страница 15: ...omputer The GPIB 1014 has the following features Complete IEEE 488 Talker Listener Controller TLC capability using the NEC PD7210 GPIB TLC chip DMA transfers Data rates up to 500 kbytes sec Unlimited...

Страница 16: ...duction Chapter 1 GPIB 1014 User Manual 1 2 National Instruments Corporation Figure 1 1 shows the GPIB 1014 interface board Figure 1 1 GPIB 1014 Interface Board Art not available in PDF version of doc...

Страница 17: ...14 boards GPIB 1014 1 776059 01 GPIB 1014 2 776060 01 GPIB 1014 EH EH Ejector Handles 776059 51 GPIB 1014 1S no P2 signals 776059 21 GPIB 1014 1S EH no P2 signals EH Ejector Handles 776059 61 One GPIB...

Страница 18: ...is shipped packaged in an antistatic plastic bag to prevent electrostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such damage in handling...

Страница 19: ...le 2 1 contains a list of the VMEbus signals used by the GPIB 1014 and the electrical loading presented by the circuitry on the interface board in terms of device types and their part numbers Note The...

Страница 20: ...AN Note The GPIB 1014 requires regulated 5 VDC power from the VMEbus Current load is typically 1 6 A 2 0 A maximum VMEbus Characteristics The following paragraphs describe each of the VMEbus modules o...

Страница 21: ...ta lines D07 through D00 The 68450 can function as an 8 or 16 bit slave allowing transfers on data lines D15 through D00 The board is designed to accommodate Address Only ADO cycles In VMEbus terminol...

Страница 22: ...s 4C R W Memory Address Register MAR1 1 32 bits 69 R W Memory Function Code MFCR1 1 8 bits 54 R W Device Address Register DAR1 1 32 bits 71 R W Device Function Code DFCR1 1 8 bits 5A R W Base Transfer...

Страница 23: ...CSR3 3 8 bits C1 R Channel Error CER3 3 8 bits C4 R W Device Control DCR3 3 8 bits C5 R W Operation Control OCR3 3 8 bits C6 R W Sequence Control SCR3 3 8 bits C7 R W Channel Control CCR3 3 8 bits ED...

Страница 24: ...s follows GPIB Data In DI Address Status Change ADSC GPIB Data Out DO Secondary Address Pass Through APT END Message Received END RX Service Request Input SRQI GPIB Command Out CO Device Execute Trigg...

Страница 25: ...r it does not have the following modules Bus Timer Arbiter Interrupt Handler IACK Daisy Chain Driver System Clock Driver Serial Clock Driver Power Monitor Diagnostic Aids The GPIB 1014 is designed to...

Страница 26: ...ctional Description In the simplest terms the GPIB 1014 can be thought of as a bus translator converting messages and signals present on the VMEbus into appropriate GPIB messages and signals Expressed...

Страница 27: ...ce B Device A VMEbus Computer with GPIB 1014 Able to Talk Listen and Control 8 Lines 5 Lines DIO1 DIO8 DAV Data Valid NRFD Not Ready for Data NDAC Not Data Accepted IFC Interface Clear ATN Attention S...

Страница 28: ...R D Lab Microprocessor Work Station Production Testing VMEbus Computer with GPIB 1014 IEEE 488 Interface IBM PC with GPIB PC IEEE 488 Interface S 100 Computer GPIB 696P IEEE 488 Interface PDP 11 44 w...

Страница 29: ...Priority Interrupt DTBArbitration Utility VMEbus Data Transceivers Control Transceivers Configuration Registers DMA Gating and Control GPIB Synchronization and Interrupt Control Address Decoding Addr...

Страница 30: ...er Implements the VMEbus priority interrupt protocol allowing the GPIB 1014 to request and respond to an interrupt acknowledge cycle All interrupt conditions are also detectable by polling DTB Control...

Страница 31: ...plete Extended Talker capability Basic Extended Talker Serial Poll TE5 Complete Extended Talker capability continued Talk Only mode Unaddressed on MSA LPAS Send END or EOS Dual primary addressing L3 C...

Страница 32: ...Poll It can be placed in a Talk Only mode and is unaddressed to talk when it receives its listen address The interface can operate as a basic Listener or Extended Listener It can be placed in a Liste...

Страница 33: ...and two Configuration Registers D16 D8 EO 8 or 16 bit data path to DMAC registers A16 Responds to 16 bit short I O addresses when specified on the address modifier lines ADO Accommodate Address Only...

Страница 34: ...to configure and install the GPIB 1014 hardware Configuration Before installing the GPIB 1014 in the VMEbus backplane the following options must be configured with hardware jumpers that are located o...

Страница 35: ...ation and Installation Chapter 3 GPIB 1014 User Manual 3 2 National Instruments Corporation Figure 3 1 shows the locations of the GPIB 1014 configuration jumpers and switches Figure 3 1 Parts Locator...

Страница 36: ...y respond to a 16 bit address and an AM code of 2D If the board is configured for User mode the board will initially respond to a 16 bit address and AM codes of 29 and 2D Refer to the ANSI IEEE Std 10...

Страница 37: ...guration for GPIB 1014 Base Address 2000 hex Default Setting Set Base Address Using Compare Address Lines Another method of setting the base address is to use the compare address lines located on the...

Страница 38: ...are found between jumper W5 and the other jumpers 0 1 1 0 U S AM1 AM1 W5 U32 C33 U33 W4 W3 68450 F245 F322 W2 Figure 3 4 Default Settings of AM Code Jumpers W3 W4 and W5 Rev D and earlier versions of...

Страница 39: ...e listed in Table 3 1 you can produce any arbitrary AM code by changing jumpers W3 W4 and W5 along with programming the DMAC Table 3 2 shows how each of the six AM code bits is affected by the jumpers...

Страница 40: ...DMA transfer mode Software control of these parameters gives you the flexibility to tailor operation and performance to meet the specific requirements of separate tasks within your system Installatio...

Страница 41: ...A03 A13 DS0 A29 A02 A14 WRITE A30 A01 A15 GND A31 12V A16 DTACK A32 5V B1 BBSY B17 AM1 B2 BCLR B18 AM2 B3 ACFAIL B19 AM3 B4 BG0IN B20 GND B5 BG0OUT B21 SERCLK B6 BG1IN B22 SERDAT B7 BG1OUT B23 GND B8...

Страница 42: ...19 D21 B4 A24 B20 D22 B5 A25 B21 D23 B6 A26 B22 GND B7 A27 B23 D24 B8 A28 B24 D25 B9 A29 B25 D26 B10 A30 B26 D27 B11 A31 B27 D28 B12 GND B28 D29 B13 5V B29 D30 B14 D16 B30 D31 B15 D17 B31 GND B16 D18...

Страница 43: ...connector and a 24 pin IEEE 488 connector A dual connector version of the scrambler card is also available for use with two GPIB 1014 2 Interface Cards The Models GPIB 1014 EH GPIB 1014 1S and GPIB 1...

Страница 44: ...ddress 113 Read only 8 bit Interrupt Mask Register 1 Base address 113 Write only 8 bit Interrupt Status Register 2 Base address 115 Read only 8 bit Interrupt Mask Register 2 Base address 115 Write onl...

Страница 45: ...rity Register Base address 2D Read Write 8 bit General Control Register Base address FF Read Write 8 bit Interrupt Vector Registers Normal Interrupt Vector Base address 25 Read Write 8 bit Error Inter...

Страница 46: ...ndicates that the signal is active low An asterisk is equivalent to an overbar In many of the registers several bits are labeled with an X indicating don t care bits When a register is read these bits...

Страница 47: ...ace registers is addressed relative to the GPIB 1014 VMEbus base address Figures 4 1 and 4 2 show the register and bit mnemonics of each TLC internal register its read write accessibility and its rela...

Страница 48: ...DI CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE INT SRQI LOK REM CO LOKC REMC ADSC 0 SRQI IE DMAO DMAI CO IE LOKC IE REMC IE ADSC IE S8 PEND S6 S5 S4 S3 S2 S1 S8 rsv S6 S5 S4 S3 S2 S1 CIC ATN...

Страница 49: ...0 is ICR is loaded with PPR is loaded with AUXRA is loaded with AUXRB is loaded with AUXRE is loaded with W AUXMR CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0 0 CLK3 CLK2 CLK1 CLK0 U S P3 P2 P1 BIN XEOS RE...

Страница 50: ...d to move data from the GPIB to the computer when the interface is a Listener The GPIB Ready For Data RFD message is held false until the byte is removed from the DIR either by a DMA transfer to the V...

Страница 51: ...O0 The Command Data Out Register CDOR is used to move data from the VMEbus to the GPIB when the interface TLC is the GPIB Talker or the Active Controller Outgoing data is separately latched by this re...

Страница 52: ...where each condition has an Interrupt Status bit and an Interrupt Enable bit associated with it If the Interrupt Enable bit is true when the corresponding status condition or event occurs a hardware...

Страница 53: ...secondary commands when the Command Pass Through feature is enabled by the CPT ENABLE bit AUXRB 0 w Any GPIB command message not decoded by the TLC is treated as an undefined command however any addr...

Страница 54: ...until either the Valid or Non Valid auxiliary command is issued The secondary address can be read from the CPTR 5r DET Device Execute Trigger Bit 5w DET IE Device Execute Trigger Interrupt Enable Bit...

Страница 55: ...e Clear Bit 3w DEC IE Device Clear Interrupt Enable Bit DEC is set by DCAS DEC is cleared by pon read ISR1 Notes DCAS GPIB Device Clear Active State pon Power On Reset read ISR1 Bit is cleared immedia...

Страница 56: ...et as TACS SGNS becomes true DO is cleared by read ISR1 TACS SGNS Notes TACS GPIB Talker Active State SGNS GPIB Source Generate State read ISR1 Bit is cleared immediately after it is read The DO bit i...

Страница 57: ...Bit is cleared immediately after it is read finish Handshake Finish Handshake auxiliary command issued Holdoff mode RFD Holdoff state read DIR Read Data In Register The DI bit indicates that the TLC...

Страница 58: ...rupt request is generated Bits in ISR2 are set and cleared regardless of the status of the bits in IMR2 If a condition occurs that requires the TLC to set or clear a bit or bits in ISR2 at the same ti...

Страница 59: ...ockout Change Bit ADSC Address Status Change Bit ADSC IE Enable Interrupt on Address Status Change Bit 7w 0 Reserved Bit Write zero to this bit 6r SRQI Service Request Input Bit 6w SRQI IE Service Req...

Страница 60: ...Remote State REMS or Remote With Lockout State RWLS The TLC RL function transfers to one of these states when the System Controller has asserted the Remote Enable line REN and the CIC addresses the T...

Страница 61: ...ELS 1r REMC Remote Change Bit 1w REMC IE Remote Change Interrupt Enable Bit REMC is set by any change in REM REMC is cleared by pon read ISR2 Notes REM ISR2 4 r pon Power On Reset read ISR2 Bit is cle...

Страница 62: ...it ADSR 2 r CIC Controller In Charge bit ADSR 7 r MJMN Major Minor bit ADSR 0 r lon Listen Only bit ADMR 6 w ton Talk Only bit ADMR 7 w pon Power On Reset read ISR2 Bit is cleared immediately after it...

Страница 63: ...l Poll Enable SPE command message the TLC transmits a byte of status information SPMR 7 0 to the Controller In Charge after the Controller goes to standby and becomes an Active Listener 6r PEND Pendin...

Страница 64: ...nal is asserted 5r SPMS Serial Poll Mode State Bit If SPMS 1 the TLC GPIB Talker T or Talker Extended TE function is able to participate in a Serial Poll SPMS is set when the TLC has been addressed as...

Страница 65: ...ommand 1r TA Talker Active Bit TA is set when the TLC has been addressed or programmed as the GPIB Talker that is the TLC is in the Talker Active State TACS the Talker Addressed State TADS or the Seri...

Страница 66: ...alker Active State TACS It is also necessary to execute the Chip Reset or Immediate Execute pon auxiliary command 6w lon Listen Only Bit By setting lon programs the TLC becomes a GPIB Listener If lon...

Страница 67: ...d Listener function should be disabled The minor Talker and Listener function can be disabled by setting the Disable Talker DT and Disable Listener DL bits in ADR1 set ADR and ADR1 In mode 2 ADM1 1 AD...

Страница 68: ...poration Bit Mnemonic Description ADM0 and ADM1 must be cleared when either of the two programmable bits ton or lon is set For more information on the different addressing modes supported by the GPIB...

Страница 69: ...3 All GPIB Secondary Command Group SCG messages following an undefined GPIB PCG message are also treated as undefined When an undefined GPIB message is encountered it is held in the CPTR and the TLC...

Страница 70: ...19 SPD Serial Poll Disable 20 3E MLA My Listen Address 3F UNL Unlisten 40 5E MTA My Talk Address 5F UNT Untalk 60 6F MSA PPE My Secondary Address or Parallel Poll Enable 70 7E MSA PPD My Secondary Add...

Страница 71: ...Mnemonic Description 7 5w CNT 2 0 Control Code Bits 2 through 0 These bits indicate the control code that is the manner in which the information in bits COM 4 0 is to be used If CNT 2 0 are all zero...

Страница 72: ...1 1 1 0F Valid Secondary Command or Address 0 0 0 0 1 01 Clear Parallel Poll Flag 0 1 0 0 1 09 Set Parallel Poll Flag 1 0 0 0 1 11 Take Control Asynchronously Pulsed 1 0 0 1 0 12 Take Control Synchro...

Страница 73: ...le State TIDS Talker Idle State TPIS Talker Primary Idle State If the command is sent while a pon message is already active by either an external reset pulse or the Chip Reset auxiliary command the lo...

Страница 74: ...is zero the message is generated in the form of a pulse When COM3 is one the rtl command is set in the standard manner 0 0 1 1 0 Send EOI SEOI The Send EOI command causes the GPIB End Or Identify EOI...

Страница 75: ...lses the local message tca 1 0 0 1 0 Take Control Synchronously The Take Control Synchronously command sets the local message tcs The local message tcs is effective only when the TLC is in Controller...

Страница 76: ...e TLC enters either Controller Parallel Poll State CPPS or Controller Idle State CIDS The transition of the TLC interface function is not guaranteed if the local messages rpp and Go To Standby gts are...

Страница 77: ...AUXMR 4 0 is loaded with the data to be transferred to the hidden register The hidden registers cannot be read and in some cases the contents are setable only that is they can be cleared or reset to...

Страница 78: ...t Write zero to this bit 3 0w CLK 3 0 Clock Bits 3 through 0 The contents of the ICR are used to divide internal counters that generate TLC state change delay times used by the IEEE 488 specification...

Страница 79: ...ividual status ist message using Set Clear Parallel Poll Flag auxiliary commands according to pre established system protocol convention Writing to the PPR after it is remotely configured will corrupt...

Страница 80: ...Poll Response Bits 3 through 1 PPR bits 3 through 1 designated P 3 1 contain an encoded version of the Parallel Poll response P 3 1 indicate which of the eight DIO lines is asserted during a Parallel...

Страница 81: ...END Bit Mnemonic Description 4w BIN Binary Bit The BIN bit selects the length of the EOS message Setting BIN causes the End Of String Register EOSR to be treated as a full 8 bit byte When BIN 0 the E...

Страница 82: ...sh Handshake FH auxiliary command is issued Unlike Normal Handshake mode the RFD HLDA mode does not generate the rdy message even if the received data is read through the DIR that is the GPIB RFD mess...

Страница 83: ...the following paragraphs Bit Mnemonic Description 4w ISS Individual Status Select Bit The ISS bit determines the value of the TLC ist message When ISS 1 ist becomes the same value as the TLC Service R...

Страница 84: ...f the first byte Clearing TRI sets the low speed timing T1 2 sec 1w SPEOI Send Serial Poll EOI Bit The SPEOI bit permits or prohibits the transmission of the END message in Serial Poll Active State SP...

Страница 85: ...0 causes the two lowest order bits to be written to AUXRE The 2 bit code DHDC and DHDT determines how the TLC may be placed into DAC Holdoff Bit Mnemonic Description 4 2w 0 Reserved Bits Write zeros t...

Страница 86: ...scription 7r X Don t Care Bit Reads as a zero or one 6r DT0 Disable Talker 0 Bit If DT0 is set it indicates that the mode 2 primary or mode 1 and 3 major Talker is not enabled that is the TLC does not...

Страница 87: ...respectively 6w DT Disable Talker Bit DT must be set if recognition of the GPIB talk address formed from AD5 through AD1 ADR 4 0 w is not to enable 5w DL Disable Listener Bit DL must be set if recogn...

Страница 88: ...ived byte EOI is cleared by pon or by using the Chip Reset auxiliary command EOI is updated after each byte is received 6r DT1 Disable Talker 1 Bit If DT1 is set the mode 2 secondary or mode 1 and 3 m...

Страница 89: ...inary can be placed in the EOSR to be used in detecting the end of a block of data The length of the EOS byte to be used in the comparison is selected by the BIN bit in AUXRA AUXRA 4w If the TLC is a...

Страница 90: ...e board address space are reserved The registers set associated with each DMA channel is shown in Table 4 7 Table 4 7 DMAC DMA Channel Register Set Register Name Mnemonic Size Memory Address Register...

Страница 91: ...F 11 13 15 17 19 1B 1D 1F 21 23 25 27 29 2B 2D 2F 31 33 35 37 39 3B 3D 3F 8 7 CSR CER MTCR MAR MSB LSB DAR MSB LSB BTCR BAR MSB LSB NIVR EIVR MFCR CPR DFCR BFCR Null Bit Position The GCR is located at...

Страница 92: ...AR in the chained modes of operation the DMAC first reads using DMA the address of the next block to be transferred into the MAR then starts the actual data transfer In most GPIB to memory transfers t...

Страница 93: ...prior to starting the channel and will be decremented with each operand transfer When the contents of this register are zero and the operation is unchained or the chain is exhausted the channel has r...

Страница 94: ...ne the 6 bit Address Modifier AM code on the VMEbus The AM codes are used to identify the type of cycle specified by the DMAC when the GPIB 1014 is the bus master Table 3 1 shows how to program bits M...

Страница 95: ...t may be used in memory to memory transfers 00 Burst Transfer Mode 10 Cycle Steal Mode 01 Undefined Reserved 11 Cycle Steal with Hold Mode 5 4r w DTYP Device Type Bits 5 through 4 The Device Type bits...

Страница 96: ...n PCL2 signal REN is connected If programmed as status inputs you can determine the state high or low of these two GPIB signals by reading the PCS bit in the appropriate CSR PCL1 is designed to detect...

Страница 97: ...mory to device 1 Transfer from device to memory In GPIB applications 0 indicates transfers from memory to GPIB and 1 indicates transfers from GPIB to memory 6r w 0 Reserved Bit Write zero to this bit...

Страница 98: ...0 The DMA Request Generation method bits define how requests for transfers are generated For the GPIB to memory DMA transfers the request mode is always 10 the REQ line initiates an operand transfer...

Страница 99: ...2r w MAC Memory Address Count Bits 3 through 2 The Memory Address Count bits indicate the count sequence of the Memory Address Register 00 Memory address does not count 01 Memory address register coun...

Страница 100: ...register cannot be reset by a write to the register The software abort bit SAB can be used to terminate the operation Setting the SAB resets the STR and CNT Setting the HLT bit halts the channel and r...

Страница 101: ...d 1 Abort channel operation Bit Mnemonic Description 3r w EINT Interrupt Enable Bit The Interrupt Enable bit in used to enable or disable interrupts from the channel GPIB 1014 interrupts are discussed...

Страница 102: ...any DMA operation This bit must be cleared to start another channel operation 0 Channel operation incomplete 1 Channel operation complete 6r w BTC Block Termination Complete Bit The Block Termination...

Страница 103: ...serted after the channel has been started The bit remains set until the channel operation terminates This bit is unaffected by write operations 0 Channel not active 1 Channel active 2r w 0 Reserved Bi...

Страница 104: ...it of the CSR indicates if there is an error Bits 0 through 4 of the CER indicate what type of error occurred Bit Mnemonic Description 7 5r 0 Reserved Bits 4 0r ERROR CODE Error Code 00000 No error 00...

Страница 105: ...ce are pending at the DMAC the channel with the highest priority receives first service Channel priority is also used to determine which channel is serviced first when multiple channels have interrupt...

Страница 106: ...propriate programmable interrupt vector on the lower eight bits of the data bus for the channel requesting an interrupt The EINT bit of the Channel Control Register CCR determines if an interrupt can...

Страница 107: ...ined to have paused if it does not make any requests during a full sample interval after the previous operand was transferred The sample interval is programmed via the GCR and is expressed in clock cy...

Страница 108: ...r bits define the following operating parameters Bit Mnemonic Description 7 5w INTRQ Interrupt Request Bits 7 through 5 The interrupt request bits are used to select one of the seven VMEbus interrupt...

Страница 109: ...ed to enable or disable the automatic carry cycle feature of the GPIB 1014 1 Carry Cycle feature enabled 0 Carry Cycle feature disabled The feature is not enabled after power up or after the board is...

Страница 110: ...it This board specific bit is used to drive the VMEbus SYSFAIL line and to control the color of the LED on the board On power up this bit is cleared the LED is red and the board drives the SYSFAIL lin...

Страница 111: ...The local reset line must be left in the active state for at least 10 msec to ensure that the onboard circuitry is reset properly 0 Local reset line inactive 1 Local reset line active VMEbus signal SY...

Страница 112: ...hine DMA Gating and Control GPIB Synchronization and Interrupt Control Interrupter DTB Requester PD7210 TLC 68450 DMAC The GPIB 1014 also has another method for initializing the circuitry on the card...

Страница 113: ...ears the status and error bits 2 The interrupt vector registers Normal Interrupt Vector Register NIVR and Error Interrupt Vector Register EIVR for all channels are set to 0x0F hex A typical programmed...

Страница 114: ...G2 is set To take control issue the Set IFC auxiliary command wait for a minimum of 100 sec and then issue the Clear IFC auxiliary command The ensuing GPIB IFC message initializes the GPIB interface f...

Страница 115: ...ait for CO to be set again and then issue the Go To Standby auxiliary command Case 2 The TLC becomes a GPIB Listener when ATN is unasserted To do this wait for CO to be set issue the TLC GPIB Listen A...

Страница 116: ...auxiliary function is active the Take Control Synchronously auxiliary command may be sent at any time When the Take Control Synchronously auxiliary command is used the TLC takes control of the GPIB on...

Страница 117: ...e the TLC GPIB Talker and Listener functions If used ton or lon should be set during TLC initialization When the TLC is GPIB Active Controller the Listen and Local Unlisten programmed auxiliary comman...

Страница 118: ...status refers to the major or minor address Address Mode 3 Address Mode 3 like Address Mode 2 is used to implement Extended GPIB Talk and Listen address recognition However unlike Address Mode 2 Addr...

Страница 119: ...ess each time If a PCG message is received before a secondary address is received the TPAS and LPAS bits are cleared Sending Receiving Messages When the TLC is a GPIB Talker or Listener data device de...

Страница 120: ...he two DMAC channels used by the GPIB 1014 are channels 0 and 1 The DMAC can be configured to transfer data between the GPIB TLC and the VMEbus system memory with or without the carry cycle feature Th...

Страница 121: ...s Similarly if BERR occurs during a DMA transfer the processor is also interrupted When the GPIB handshake is synchronized the system is also interrupted and you can check the COC and ERR bit in the C...

Страница 122: ...to transfer multiple blocks of data e Write to the SCR of Channel 0 The MAC bits must be set to determine if the MAC counts up or down binary 01 Up binary 10 Down The DAC bits are not used f If no cha...

Страница 123: ...Channel 1 to enable interrupts Load the NIVR and EIVR of Channel 1 with the proper status ID byte to return to the VMEbus interrupt handler b If VMEbus interrupts are not used complete the following e...

Страница 124: ...ined earlier in this chapter Channel 1 is set up to transfer two tiny blocks of data It is easiest to use the array chaining mode on Channel 1 however linked chaining is also possible Channel 1 can al...

Страница 125: ...g is used to transfer a block of data greater than 64K or to transfer multiple blocks of data e The SCR of Channel 0 is written to Set the MAC bits to determine if the MAC counts up or down 01 Up 10 D...

Страница 126: ...leftover error or status bits c Load the DCR of Channel 1 with the proper value to select the DMA transfer mode cycle steal without hold or cycle steal with hold Set the DTYP bits to 10 device with A...

Страница 127: ...rry cycle byte is the command that is to be written to the AUXMR of the TLC send EOI RFD Holdoff on ALL and so on This byte must be located somewhere in memory where it can be accessed by the DMAC The...

Страница 128: ...ecking the Result If either Channel 0 or 1 is improperly programmed the ERR bit in the CSR of the active channel is set by the DMAC and the CER of the channel indicates a configuration error The follo...

Страница 129: ...the CSR of Channel 0 A timeout error no interrupt occurs if Channel 0 is improperly programmed If the PCT bit in Channel 1 is set and there are no errors on Channel 0 or 1 one of the following events...

Страница 130: ...n the board which generates the GPIB handshake synchronization status signal 6 If a GPIB error occurred during the transfer ERR bit set in the TLC s ISR1 poll the BTAC and MTCR of the DMAC until you a...

Страница 131: ...CDOR The DO bit is set again once that byte has been received by all Listeners To receive data wait until the TLC has been programmed or addressed to listen and the DIR is full When this occurs the DI...

Страница 132: ...terrupt on any of the following conditions An interrupt request is received from the GPIB TLC A bus error occurs during a DMA transfer A DMA transfer from memory to the GPIB is complete and the GPIB i...

Страница 133: ...lly not enabled on Channel 0 If triggered all three interrupt events mentioned earlier will cause the set PCT bit to indicate a PCL transition and an interrupt A bus error that occurs when Channel 1 i...

Страница 134: ...plete before asserting the GPIB SRQ signal In response to that signal the CIC starts the poll addressing the TLC to talk When the CIC unasserts ATN the TLC unasserts SRQ and transfers the STB message...

Страница 135: ...nd how that device drives the line depends upon how it was configured and whether its local individual status message ist is one or zero Thus each device on the GPIB can be configured to drive its ass...

Страница 136: ...local configuration PP2 the three actions listed above must be explicitly handled in the software by writing the appropriate values to the U S and P3 to P1 bits of the PPR Refer to the PPR description...

Страница 137: ...evice signals CLR clear and PR preset VMEbus Interface Address data control and status signals to or from the VMEbus are buffered with LSTTL ASTTL or FTTL logic devices All drivers drive the proper am...

Страница 138: ...that is it does not have control of the bus control signals are directly routed onboard In contrast during DMA cycles control signals from the DMAC are somewhat altered before passing out to the VMEb...

Страница 139: ...EN ACKEN DBEN NEW_CYCLE BRDEN DS HIBYTE DIR BWR OWN BWR OWN Address Decoding During non DMA operations the GPIB 1014 acts as a VMEbus slave and monitors the lower 16 lines of the VMEbus address bus A1...

Страница 140: ...register select lines RS2 through RS0 The TLC functions as an 8 bit slave It transfers data on the lower eight bits of the VMEbus data bus The TLC registers are located at consecutive odd addresses a...

Страница 141: ...egisters Two registers CFG1 and CFG2 are 8 bit write only registers used by the controlling software program application program and or interface handler to configure some of the operating characteris...

Страница 142: ...TB Requester circuitry Selecting the direction of the DMA transfer Writing a 1 to this bit DIR indicates that the transfer direction is from GPIB to VMEbus memory while writing a zero indicates that t...

Страница 143: ...he GPIB 1014 is used to automatically determine the state of this bit SUP after a system or local reset After reset you can write a 1 to this bit to select Supervisor only access or a 0 to select User...

Страница 144: ...fer for the TLC by driving either ACK0 or ACK1 low The Timing State Machine also starts when this is detected When the transfer is from the TLC to the VMEbus memory the DMAC drives the VMEbus WRITE li...

Страница 145: ...red by the DMAC to the TLC auxiliary register Since the TLC does not allow DMA transfers to the auxiliary register discrete circuitry must make this cycle appear as a normal write cycle to the TLC Fur...

Страница 146: ...errupt priority code in CFG1 If IACKIN is asserted and the indicated priority does not match the GPIB 1014 priority the daisy chain signal IACKOUT is asserted This signal remains asserted until AS is...

Страница 147: ...lines In addition the circuitry uses three flip flops to keep status of the bus arbitration process that is bus request pending bus grant received and bus release and uses miscellaneous logic to gene...

Страница 148: ...been granted the bus BGIN asserted BGACK is released as soon as BBSY is released by another master on the VMEbus While the GPIB 1014 is holding the bus BGACK will be released at all times If a pending...

Страница 149: ...steal mode it releases OWN immediately after it has finished the DMA transfer In contrast if the DMAC operates cycle steal with hold mode it keeps asserting OWN during the hold period and releases OWN...

Страница 150: ...er sequence If the carry cycle was not enabled as indicated by the CC bit in CFG1 the last byte is detected by DONE and ACK0 which are both active at the same time DMAC asserts DONE when Channel 0 is...

Страница 151: ...Channel 0 but enable interrupts on Channel 1 A negative transition on the PCL of Channel 1 occurs if the GPIB is synchronized requesting an interrupt at this point Channel 0 is already complete Since...

Страница 152: ...s 0 and 1 to provide GPIB to memory DMA flyby transfers All four channels are available for general use such as memory to memory DMA transfers The DMAC provides 24 bit addressing a 16 bit data path an...

Страница 153: ...evice Control Register DCR The DTYP bits of the DCR define what type of device is on the channel If the DTYP bits are programmed to be a HMCS6800 device the PCL definition is ignored and the PCL is an...

Страница 154: ...quest is not present during the hold period the DMAC relinquishes the bus by unasserting its signal OWN The sample period is defined by the values programmed into the GCR Data Transfers All DMAC trans...

Страница 155: ...o count up down or not change and whether the transfer is explicitly or implicitly addressed The Sequence Control Register SCR is used to program the memory address count method and the device address...

Страница 156: ...t in the CSR Any pending requests are cleared and the channel is then ready to receive requests for the new operation If the channel is configured for an illegal operation the configuration error is s...

Страница 157: ...f this counter is decreased to the terminal count the MTCR is exhausted and the operand is the last operand of the block The channel operation is complete if the operation is unchained and there is no...

Страница 158: ...er Counter BTCR that is the BAR points to the address transfer count array Before starting any block transfers the DMAC fetches the entry a total of six bytes in three DMA cycles currently pointed to...

Страница 159: ...is placed in the MTCR and the link address replaces the current contents of the BAR The channel then begins a new block transfer As each chaining entry is fetched the updated BAR is examined for the t...

Страница 160: ...mory Address B Transfer Count B Link to next entry Memory Address B Transfer Count B 0000 end link Figure 6 3 Array Format for Linked Chaining Modes Error Conditions When an error is signaled on a cha...

Страница 161: ...pt is made to write to the DCR OCR SCR GCR MAR DAR or MTCR with STR or ACT asserted if an attempt to assert CNT is made when CHN is 10 or 11 or if an attempt to assert CNT is made when BTC and ACT are...

Страница 162: ...the DMAC Instead the chip is enabled and selected by the DMAACK DMA Acknowledge signal and the TLC internal registers CDOR and DIR are automatically accessed Data is strobed into the CDOR at the risi...

Страница 163: ...re switched to Open Collector mode Test and Troubleshooting The GPIB 1014 is designed to aid acceptance testing and troubleshooting of either hardware failures or software bugs The hardware provides s...

Страница 164: ...signals can be manipulated properly NDAC is the GPIB Not Data Accepted signal By programming the TLC to Listen or not Listen via the AUXMR NDAC can be asserted or not asserted respectively DIO1 is the...

Страница 165: ...tions The left side of the equation contains the hexadecimal address offset from the GPIB 1014 base address and mnemonic for the register The right side of the equation contains a hexadecimal value Co...

Страница 166: ...tact National Instruments GPIB 1014 Hardware Installation Tests 1 Initialize TLC 105 CFG2 0A Set LMR and turn the LED green 105 CFG2 08 Clear LMR 11B AUXMR 2 TLC Reset 11B AUXMR 0 Immediate execute po...

Страница 167: ...SR1 2 DO 111 CDOR 51 write data byte 11B CPTR 51 verify 113 ISR1 6 DO ERR 113 ISR1 0 bits cleared when read 11B AUXMR 2 TLC Reset 119 ADMR 0 disable ton 11B AUXMR 0 Immediate execute pon 119 ADSR 40 n...

Страница 168: ...R1 FF Clear bits channel 1 11B AUXMR 2 TLC Reset 11B AUXMR A0 Clear INV 119 ADMR 80 ton 113 IMR1 2 DO IE 11B AUXMR 0 Immediate execute pon 040 CSR1 2 PCL transition occurred 113 ISR1 2 DO 040 CSR1 3 T...

Страница 169: ...ata put data byte in memory 101 CFG1 18 BRG3 OUT enable ROR feature 11B AUXMR 2 TLC Reset 119 ADMR C0 ton lon 007 CCR0 80 Start channel 0 115 IMR2 20 DMA out enable 11B AUXMR 0 Immediate execute pon T...

Страница 170: ...has been transferred from TLC to memory 101 CFG1 18 clear GPIB synchronization detecting circuitry also to pull PCL1 high 040 CSR1 02 clear PCT bit in CSR1 040 CSR1 01 PCT bit cleared PCL1 high 13 Tes...

Страница 171: ...1 DO is cleared here because a byte has been transferred from memory to TLC s CDOR TLC does not currently request for DMA transfer 111 CDOR 1 check the first data byte that was transferred from memory...

Страница 172: ...C 044 DCR1 A0 005 OCR0 82 045 OCR1 8A 006 SCR0 04 046 SCR1 04 029 MFC0 06 00C MAR0 00003000 4 byte address of the first two data bytes 00A MTC0 0002 two data bytes 069 MFC1 06 079 BFC1 06 05C BAR1 000...

Страница 173: ...is full TLC will request for a DMA transfer to put the byte in DIR to memory 04A MTC1 0001 count of 1 indicates last data byte has been transferred 040 CSR1 0A GPIB synchronized 047 CCR1 10 software...

Страница 174: ...Characteristic Specification Transfer Rates DMA Over 500 kbytes sec Programmed I O Over 80 kbytes sec Power Requirement 5 VDC 1 6 A typical 2 0 A maximum Actual speed may vary considerably from those...

Страница 175: ...GPIB 1014 User Manual A 2 National Instruments Corporation Table A 3 Physical Characteristics Characteristic Specification Dimensions 6 3 in by 9 2 in I O Connector GPIB 1014 1S IEEE 488 Standard 24 p...

Страница 176: ...National Instruments Corporation B 1 GPIB 1014 User Manual Appendix B Parts List and Schematic Diagrams This appendix contains the parts list and schematic diagrams for the GPIB 1014...

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Страница 185: ...ss GPIB control to another device PASSC Assumptions regarding the state of the GPIB 1014 appear at the beginning of each routine and must be adhered to for proper error free operation The following ch...

Страница 186: ...dress Register 0 read ADR BASE 0x11D Address Register write ADR1 BASE 0x11F Address Register 1 read EOSR BASE 0x11F End Of String Register write MTC0 BASE 0x00A Channel 0 Memory Transfer Count MAR0 BA...

Страница 187: ...Auxiliary Register A AUXRB 0240 Auxiliary Register B AUXRE 0300 Auxiliary Register E AUXMR Commands IEPON 000 Immediate execute power on FH 003 Finish release handshake GTS 020 Go to standby TCA 021 T...

Страница 188: ...eal DMA transfer mode set to 340 if Cycle Steal with Hold is desired BRG 030 Bus Request BR3 selected other options are BR2 020 BR1 010 BR0 000 ADMC 06 Address Modifiers set to 24 bit supervisor acces...

Страница 189: ...timing is used Interrupts are not used Status byte will be set elsewhere Remote Parallel Poll configuration will be used Actions Pulse LMR to put hardware in known reset state Disable interrupts and c...

Страница 190: ...egisters tstb ISR2 movb MODE1 TRM ADMR Set address mode Talker Listener inactive and proper T R signal mode movb MA SEL0 ADR Set GPIB address mode 1 primary only with Talker Listener enabled movb DT1...

Страница 191: ...been initialized GPIB 1014 is System Controller SC is true Actions Assert GPIB IFC Wait at least 100 microseconds Unassert IFC Status on return GPIB 1014 is Active Controller Interface functions of o...

Страница 192: ...f REN is to be asserted and is zero if REN is to be unasserted GPIB 1014 is System Controller and Active Controller Actions Check sre flag if non zero true send REN else send clear REN Status on retur...

Страница 193: ...e number of bytes sent is less than the byte count The d0 register contains the byte count The a0 register contains the address of the data buffer The user specified variable cic is set properly Actio...

Страница 194: ...DA ccary First ccary address points to HLDA movw d0 d1 Set channel 0 transfer count subw 1 d1 to transfer all but the last movw d1 MTC0 byte movl a0 d2 Second ccary address points to addl d2 d1 last d...

Страница 195: ...r of bytes transferred bne RCV5 movw MTC0 d1 subw d1 d0 btst ECC CFG1 If carry cycle MTC0 was initialized to d0 1 beq RCV6 subw 1 d0 bra RCV6 RCV5 btst ECC CFG1 If no carry cyle leave d0 as is bne RCV...

Страница 196: ...to 1 The buffer datbuf is free to place incoming data The number of bytes to read is placed in datct Actions Set up cmdbuf and cmdct and call CMD to address the Talker and unaddress all other devices...

Страница 197: ...Talker movb LTN AUXMR Program GPIB 1014 to be a Listener movb GTS AUXMR so it can take control synchronously later then go to standby and drop ATN movw datct d0 Preset d0 register with byte count mov...

Страница 198: ...he d0 register contains the byte count The a0 register contains the address of the data buffer The user specified variable veoi has been set properly Actions Configure DMA channel 0 Clear DMAC status...

Страница 199: ...but the subw 1 d1 last data byte movw d1 MTC0 movl ccary BAR1 Point channel 1 to ccary movw 2 BTC1 2 elements in ccary movl SEOI ccary First ccary address points to SEOI movl a0 d2 Second ccary addres...

Страница 200: ...SEND4 btst COC CSR0 Calculate number of bytes transferred bne DSEND5 movw MTC0 d1 subw d1 d0 btst ECC CFG1 beq DSEND6 subw 1 d0 bra DSEND6 DSEND5 btst ECC CFG1 bne DSEND6 movw MTC1 d1 subw d1 d0 addw...

Страница 201: ...The data to be sent is placed in datbuf The variable datct contains the number of bytes to send Actions Set up cmdbuf and cmdct and call CMD to address the GPIB 1014 as Talker to address the Listener...

Страница 202: ...vb MA 100 cmdbuf 2 movb ola cmdbuf 3 bsr CMD Call CMD to address GPIB devices movb GTS AUXMR Go to standby and drop ATN movw datct d0 Preset d0 register with byte count movl datbuf a0 Preset a0 regist...

Страница 203: ...ty Write a byte and increment the counter Check for a GPIB error Loop until all bytes are transferred On an error set d0 to 1 Status on return d0 register contains number of bytes sent or 1 if an erro...

Страница 204: ...6 Interruption of any data transfer in progress is acceptable Actions Issue TCA command to assert ATN in case the GPIB 1014 is at standby Load the d0 register with the address of cmdbuf Load a0 with t...

Страница 205: ...adr Actions Send TCA command to take control in case the GPIB 1014 is at standby Set up the command buffer and command count Call CMD to send the command bytes Status on return The GPIB 1014 is Idle C...

Страница 206: ...to the interface functions These functions include initializing the bus addressing and unaddressing devices and setting device modes for local or remote programming The multiline interface messages a...

Страница 207: ...0E 016 14 SO 2E 056 46 MLA14 0F 017 15 SI 2F 057 47 MLA15 10 020 16 DLE 30 060 48 0 MLA16 11 021 17 DC1 LLO 31 061 49 1 MLA17 12 022 18 DC2 32 062 50 2 MLA18 13 023 19 DC3 33 063 51 3 MLA19 14 024 20...

Страница 208: ...55 109 m MSA13 PPE 4E 116 78 N MTA14 6E 156 110 n MSA14 PPE 4F 117 79 O MTA15 6F 157 111 o MSA15 PPE 50 120 80 P MTA16 70 160 112 p MSA16 PPD 51 121 81 Q MTA17 71 161 113 q MSA17 PPD 52 122 82 R MTA18...

Страница 209: ...ions are actually data messages Talkers Listeners and Controllers A Talker sends data messages to one or more Listeners The Controller manages the flow of information on the GPIB by sending commands t...

Страница 210: ...Charge CIC Active control can be passed from the current CIC to an idle Controller Only one device on the bus the System Controller can make itself the CIC The GPIB interface board is usually the Sys...

Страница 211: ...ommands and the Talker drives it when sending data messages Interface Management Lines Five lines are used to manage the flow of information across the interface ATN attention The Controller drives AT...

Страница 212: ...phenol or Cinch Series 57 Microribbon or Amp Champ type An adapter cable using a non standard cable and or connector is used for special interconnection applications The GPIB uses negative logic with...

Страница 213: ...Appendix E Operation of the GPIB National Instruments Corporation E 5 GPIB 1014 User Manual Figure E 2 Linear Configuration...

Страница 214: ...ate that the GPIB was designed for the physical distance between devices and the number of devices on the bus are limited The following restrictions are typical A maximum separation of 4 m between any...

Страница 215: ...ted Documents For more information on topics covered in this section consult the following manuals ANSI IEEE Std 488 1978 IEEE Standard Digital Interface for Programmable Instrumentation ANSI IEEE Std...

Страница 216: ...functions remote messages local messages states bits registers integrated circuits system functions and VMEbus operations and signals The mnemonic types in the key that follows are abbreviated to mean...

Страница 217: ...ts 1 through 0 ADMR R Address Mode Register ADO VBO Address Only Cycle ADR R Address Register ADR0 R Address Register 0 ADR1 R Address Register 1 ADSC B Address Status Change ADSC IE B Address Status...

Страница 218: ...Appendix F Mnemonics Key National Instruments Corporation F 3 GPIB 1014 User Manual BG 0 3 OUT VBS Bus Grant Out Lines BIN B Binary Bit BLT VBO Block Transfer BR 0 3 VBS Bus Request Lines...

Страница 219: ...Pass Through Enable Bit CPT IE B Enable Interrupt on Command Pass Through Bit CPTR R Command Pass Through Register CPT 7 0 B Command Pass Through Bits 7 through 0 CPWS ST Controller Parallel Poll Wait...

Страница 220: ...Memory Access DMAI B DMA Input Enable Bit DMAO B DMA Out Enable Bit DO B Data Out Bit DO IE B Enable Interrupt on Data Out Bit DS0 VBS Data Strobe Zero DS1 VBS Data Strobe One DT F Device Trigger DT B...

Страница 221: ...terrupt Acknowledge In IACKOUT VBS Interrupt Acknowledge Out IB 1 3 LS Interrupt Priority Code Bits ICR R Internal Counter Register IDTACK LS Interrupt DTACK IDY RM Identify IFC RM Interface Clear IMR...

Страница 222: ...le Interrupt on Lockout Change Bit lon B Listen Only Bit lon LM Listen Only LPAS B Listener Primary Addressed State Bit LPAS ST Listener Primary Addressed State lpe LM Local Poll Enabled lpe LM Local...

Страница 223: ...IS ST Parallel Poll Idle State PPR RM Parallel Poll Response PPSS ST Parallel Poll Standby Active PPU RM Parallel Poll Unconfigure PUCS ST Parallel Poll Unaddressed to Configure State R RD LS TLC Read...

Страница 224: ...nterface Clear Not Active State SIWS ST Source Idle Wait State SNAS ST System Control Not Active State SP F Serial Poll scanning flags SPAS ST Serial Poll Active State T function SPD RM Serial Poll Di...

Страница 225: ...chronously tcs LM Take Control Synchronously tcse LM Take Control Synchronously on End TCT TM Take Control TDMA SX Terminate DMA TE F Extended Talk TIDS ST Talker Idle State TLC IC Talker Listener Con...

Страница 226: ...nconfigure Bit UAT VBO Unaligned Transfer UCG RM Universal Command Group UDPCF LM Undefined Primary Command Function UNL RM Unlisten command UNT RM Untalk command V V 0 7 LS Interrupt Vector Bits W WR...

Страница 227: ...questions to us at any time Technical Support Phone 512 795 8248 Technical Support Fax 512 794 5678 Branch Offices Phone Number Fax Number Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0...

Страница 228: ...ficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary...

Страница 229: ...M Software Version Number on Distribution Medium National Instruments board installed GPIB 1014 GPIB 1014D GPIB 1014P or GPIB 1014DP _________________________________________________________ GPIB 1014...

Страница 230: ...Type of other boards installed and their respective hardware settings Board Type Base I O Address Interrupt Level DMA Channel...

Страница 231: ...ch 1997 Part Number 370945A 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank y...

Страница 232: ...an or equal to is greater than or equal to degrees A amperes ANSI American National Standards Institute C Celsius FCC Federal Communications Commission GPIB General Purpose Interface Bus hex hexadecim...

Страница 233: ...59 AD5 0 through AD1 0 Mode 2 Primary GPIB Address Bits 5 0 through 1 0 4 42 AD5 1 TLC GPIB Address Bit 5 through 1 4 42 AD 5 1 1 1 Mode 2 Secondary TLC GPIB Address Bits 5 1 through 1 1 4 44 address...

Страница 234: ...t 4 9 to 4 10 array chaining operations 6 19 to 6 20 ARS Address Register Select Bit 4 43 ATN Attention Bit 4 20 ATN attention line E 3 auxiliary commands detailed description 4 29 to 4 32 summary tab...

Страница 235: ...4 29 CHN Chain Bits 3 through 2 4 53 CIC Controller In Charge Bit 4 20 Clear IFC command codes for 4 28 description 4 32 Clear Parallel Poll Flag command codes for 4 28 description 4 31 Clear REN comm...

Страница 236: ...ap 4 2 theory of operation 6 5 to 6 6 control equations of transceivers 6 3 Controller function becoming controller in charge CIC and active controller 5 3 Controller In Charge CIC and System Controll...

Страница 237: ...n DTAS Bit 4 41 DI 7 0 Data In Bits 7 through 0 4 6 DI Data In Bit 4 12 to 4 13 DI IE Data In Interrupt Enable Bit 4 12 to 4 13 DIR See Data In Register DIR DIR Direction Bit 4 53 4 65 Disable System...

Страница 238: ...sters 4 62 Memory Address Register MAR 4 48 Memory Transfer Counter Register MTCR 4 48 Operation Control Register OCR 4 53 to 4 54 overview 4 46 to 4 48 register map 4 2 register memory map 4 47 Seque...

Страница 239: ...ata Out Interrupt Enable Bit 4 12 documentation abbreviations used in the manual vi related documents vi to vii E 7 don t care bits 4 3 See also X Don t Care Bit DPS Device Port Size Bit 4 51 DT Disab...

Страница 240: ...rror Interrupt Enable Bit 4 11 to 4 12 ERROR CODE Channel Error Register 4 60 error conditions DMAC channel operation 6 21 to 6 22 Execute Parallel Poll command codes for 4 28 description 4 32 F featu...

Страница 241: ...2 9 GPIB Controller See Controller function GPIB Synchronization and Interrupt Control definition of 2 12 theory of operation 6 12 to 6 14 GPIB TLC See Talker Listener Controller TLC GTL Go To Local c...

Страница 242: ...interface clear E 3 overview E 3 REN remote enable E 3 SRQ service request E 3 interface registers Address Mode Register ADMR 4 22 to 4 24 Address Register ADR 4 43 Address Register 0 ADR0 4 42 Addres...

Страница 243: ...liance levels 2 15 programming considerations 5 20 to 5 21 theory of operation 6 9 INTRQ Interrupt Request Bits 7 through 5 4 64 INV Invert Bit 4 39 ISR1 See Interrupt Status Register 1 ISR1 ISR2 See...

Страница 244: ...Register MAR 4 48 Memory Transfer Counter Register MTCR 4 48 messages multiline interface command messages D 1 to D 2 types of E 1 MJMN Major Minor Bit 4 21 MLA My Listen Address command 4 26 mnemoni...

Страница 245: ...hysical and electrical characteristics description of 2 1 to 2 2 E 4 GPIB connector and signal assignments illustration E 4 linear configuration illustration E 5 specifications A 1 star configuration...

Страница 246: ...TE ENABLE REN C 8 WRITE C 17 to C 18 sending receiving messages DMA transfers with carry cycle 5 13 to 5 17 DMA transfers without carry cycle 5 10 to 5 12 overview 5 8 polling during DMAs 5 17 sending...

Страница 247: ...ters 4 64 to 4 67 Device Address Register BAR 4 48 Device Control Register 4 51 to 4 52 DMAC DMA channel register set chart 4 46 Function Code Registers 4 50 General Control Register 4 63 Interrupt Ve...

Страница 248: ...D on EOS Received Bit 4 37 REQG DMA Request Generation Bits 1 through 0 4 54 reset See system reset Return to Local rtl command codes for 4 28 description 4 30 RFD Holdoff mode 4 38 RFD Ready for Data...

Страница 249: ...on END or EOS 5 20 Sequence Control Register SCR 4 55 Serial Poll Mode Register SPMR 4 19 Serial Poll Status Register SPSR 4 19 serial polls conducting 5 22 responding to 5 22 Set IFC command codes f...

Страница 250: ...OI Send Serial Poll EOI Bit 4 40 SPMR See Serial Poll Mode Register SPMR SPMS Serial Poll Mode State Bit 4 20 SPSR See Serial Poll Status Register SPSR SRQ service request line E 3 SRQI Service Reques...

Страница 251: ...ecking results 5 17 to 5 19 using direct memory access 5 8 to 5 19 using programmed I O 5 19 to 5 20 VMEbus slave addressing 2 2 to 2 3 TCT Take Control command 4 25 Technical support vii test and tro...

Страница 252: ...4 22 TPAS Talker Primary Addressed State Bit 4 21 transceivers for GPIB 1014 component designations 2 2 control equations of transceivers 6 3 Transfer Count Registers Base Transfer Counter Register B...

Страница 253: ...r Address command codes for 4 28 description 4 30 verification of system compatibility 3 7 to 3 9 testing 3 10 VMEbus 68450 internal DMA registers chart 2 4 to 2 5 address 6 2 control equations of tra...

Страница 254: ...Index GPIB 1014 User Manual Index 23 National Instruments Corporation X X Don t Care Bit 4 42 4 50 XEOS Transmit END with EOS Bit 4 37 XRM External Request Mode Bits 7 through 6 4 51...

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