Chapter 6
Theory of Operation
© National Instruments Corporation
6-13
GPIB-1014 User Manual
4. The outputs of the 74S139 are connected to four 74LS02 gates, along with the LBROUT*
signal, to assert one of the four VMEbus bus request lines (BR3* through BR0*).
5. The DTB Requester waits for the appropriate Bus Grant In line (BG3IN* through BG0IN*)
to become active, at which time BGIN becomes high.
6. The 74S139 outputs are used to direct the others to the corresponding Bus Grant Out line
(BG3OUT* through BG0OUT*).
If BGIN is high and the DMAC has no bus request pending, BGMATCH* is not asserted
(BUS_REL* is asserted to prevent flip-flop Q2 to change state) and the appropriate Bus Grant
Out line is driven low. This line is released when the Bus Grant In line is released. If, however,
the DMAC has a bus request pending, flip-flop Q2 changes state and BG* is asserted to inform
the DMAC that it has been granted the bus. BGMATCH* is also asserted to maintain the
BGXOUT* high. As soon as the VMEbus signal BBSY* is detected high, the DMAC asserts its
signal OWN* to start the DMA cycle. (BBSY* and OWNBUS* are both asserted). Notice that
BGIN is delayed 25 nsec by a digital delay line before its output is used to create onboard signals
BGMATCH* and BG*. This delay prevents fluctuation on Q2 output from momentarily
asserting BGMATCH* or BG*.
When the DMAC finishes the DMA transfer and wishes to relinquish the bus, it first unasserts its
OWN* signal (at this time both LBROUT* and BR* are high). The DTB Requester then
releases the VMEbus BBSY* immediately if the Release On Request feature is not enabled
(ROR*=1 & BUS_REL*=0). If the DMAC operates in cycle steal mode, it releases OWN*
immediately after it has finished the DMA transfer. In contrast, if the DMAC operates cycle
steal with hold mode, it keeps asserting OWN* during the hold period and releases OWN* if the
onboard TLC does not request DMA within the hold time. If the Release On Request feature is
enabled in CFG1 (ROR*=0), however, the DTB Requester circuitry monitors the four VMEbus
bus request lines (BR3*-BR0*). If none of these lines is logic zero, indicating that no other
device is requesting the bus (BRIN=0), the DTB Requester simply holds the bus by continuing to
drive the BBSY* line low, even when the OWN* signal of the DMAC is unasserted. If any of
the VMEbus Bus Request lines are driven low (BRIN=1) before the DMAC indicates that it
needs the bus again, BUS_REL* is asserted and the circuitry relinquishes the system bus by
releasing the BBSY* line. The DTB Requester performs the entire bus arbitration protocol the
next time the DMAC requests the bus. If, however, the DMAC requests the bus while the DTB
Requester still has control of the bus, the DMAC is immediately granted the bus and the bus
arbitration overhead is avoided.
GPIB Synchronization and Interrupt Control
This circuitry is designed to allow the GPIB-1014 to detect GPIB synchronization and control
interrupts routed to the PCL input line of DMAC Channel 1. Using the GPIB synchronization
circuitry, the GPIB-1014 can detect when the last byte of data in a data transfer has been
accepted by all devices on the GPIB. In this manner, the host CPU can be notified that the DMA
transfer is complete and does not have to timeout to ensure that the GPIB is synchronized.
The interrupt control circuitry consists of three inputs from the NOR gate and several other
miscellaneous gates. The output of the NOR gate is tied to the PCL input line of Channel 1.
