Theory of Operation
Chapter 6
GPIB-1014 User Manual
6-22
© National Instruments Corporation
If the interrupt bit in the CCR is set when the BTC bit is set, an interrupt is generated. The
interrupt handler can reload the BFCR, BAR, and BTCR with information describing the next
data block if necessary, clear the BTC bit and set the CNT to repeat the operation. In all cases, if
the MTCR is loaded with a terminal count, the count error is signaled. The GPIB-1014 usually
does not use continue operations for its GPIB DMA transfers.
Array Chaining Operations. Chaining is not necessary when transferring a single small block of
data. When data to be transferred is fragmented or is larger than 64K, array chaining is used to
transfer these blocks of data. This type of chaining uses an array in memory that holds the
addresses and transfer counts of the data blocks. The address & transfer count array must
occupy continuous memory locations. Each entry in the array is six bytes long–four bytes to
hold the starting address of a data block and two bytes to hold the length of the data blocks. The
beginning address of this array is in the Base Address Register (BAR), and the number of entries
in the array is in the Base Transfer Counter (BTCR)–that is, the BAR points to the address &
transfer count array. Before starting any block transfers, the DMAC fetches the entry (a total of
six bytes in three DMA cycles) currently pointed to by the BAR. The address information is
placed in the MAR and the count information is placed in the MTCR. After each chaining entry
is fetched, the BTCR is decremented by one and the BAR is incremented by six to point to the
next entry. When the BTCR reaches a terminal count, the chain is exhausted, and the entry just
fetched determines the last block of the the channel operation. After this data block is
transferred, the channel operation is completed and the COC bit will be set.
As described in Chapter 5, Programming Considerations, the array chaining mode is used for
Channel 1 in the GPIB-1014 applications to implement the carry cycle feature. It is also used to
transfer multiple blocks of data on Channel 0.
The address & transfer count array must start at an even address, or the entry fetch results in an
address error. The transfer count (the last two bytes of each array entry) must be non-zero. The
starting address (the first four bytes of each array entry) can be even or odd. Since the base
registers can be read by the CPU, appropriate error recovery information is available should the
DMAC encounter an error anywhere in the chain. An example of the array format for array
chaining is shown in Figure 6-2.
