Theory of Operation
Chapter 6
GPIB-1014 User Manual
6-14
© National Instruments Corporation
This PCL is used to detect interrupts from the GPIB-1014 that are not internal to the DMAC. A
negative transition on the PCL sets the PCT bit in the CSR of DMAC Channel 1. If interrupts
are enabled in the CCR of Channel 1 (EINT=1), the setting of the PCT bit causes the DMAC to
drive its IREQ* line, requesting an interrupt. The three inputs of the NOR gate enable the
negative transition to occur if the TLC requests an interrupt, if a bus error occurs while the
DMAC is the bus master, or when the GPIB becomes synchronized after the last DMA transfer
has finished.
The INT pin of the TLC is connected to one of the inputs of the NOR gate. Each of the TLC
interrupt request events or conditions are controlled by mask bits located within the TLC. Each
of the 13 events is individually enabled by bits in the mask registers IMR1 and IMR2. If the
TLC detects an interrupt condition, it drives its INT pin high. This action causes a negative
transition on DMAC Channel 1 PCL, which sets the PCT status bit and generates an interrupt if
interrupts are enabled. The interrupt condition can be detected by polling the TLC interrupt
status registers. Reading from the appropriate status register releases the TLC INT line and
enables further interrupts. Notice that the TLC must be properly configured in order to present
an active high interrupt request output. This is accomplished by clearing the INV bit of
AUXRB.
The GPIB synchronization circuitry consists of two LS74A flip-flops and various logic gates.
The circuitry detects GPIB synchronization after the last byte in a DMA transfer has been
transferred to or from the TLC. This is accomplished by monitoring the DAV* line on the GPIB.
The circuitry begins when the ALLDONE signal becomes high, which occurs during the last data
byte transfer in the DMA transfer sequence. If the carry cycle was not enabled (as indicated by
the CC bit in CFG1), the last byte is detected by DONE* and ACK0*, which are both active at
the same time. DMAC asserts DONE* when Channel 0 is transferring the last data byte in the
last data block in Channel 0 chain. ALLDONE is driven high during this time. If a carry cycle
was enabled and the carry cycle byte was sent (as indicated by the flip-flop in the DMA Gating
circuitry being set), the next DMA cycle to transfer the last data byte (indicated by ACK1*
asserted) make signal ALLDONE high. After this last data transfer, DMAREQ from TLC is
masked (see DMA Gating and Control earlier in this chapter) and Channel 1 is still active (see
Chapter 5, Programming Considerations); thus, Channel 1 cannot reach its terminal count. In
both cases, the positive transition (0 to 1) in ALLDONE causes the GPIB synchronization
circuitry to begin monitoring the GPIB DAV* line.
The GPIB synchronization is detected differently depending upon the direction of the DMA
transfer. The direction of the transfer is specified in the DIR bit in CFG1. If the transfer is from
the VMEbus memory to the GPIB (DIR = 0), the ALLDONE signal indicates that the last byte
has just been transferred to the TLC. The DAV* line at this time is high. The TLC drives
DAV* low as it places the data on the GPIB. As soon as all Listeners have accepted the byte, the
TLC releases DAV* to high again. It is this positive transition of the DAV* line that is of
interest. A D-type flip-flop, with the DAV* line as the clock input, is set by the DAV* low-to-
high transition. This generates a negative transition on the PCL of DMAC Channel 1.
If the direction of the DMA transfer is from the GPIB to the VMEbus system memory (DIR =1),
the GPIB synchronization is detected by watching the level of the DAV* line rather than looking
for a transition. The ALLDONE signal indicates that the last byte in the DMA transfer has just
been transferred from the TLC. This means that the TLC has already accepted the byte from the
GPIB. By the time the DMA transfer is complete, all devices on the GPIB may have already
