Programming Considerations
Chapter 5
GPIB-1014 User Manual
5-22
© National Instruments Corporation
The TLC contains its own internal registers, which are used to control and enable interrupts. The
interrupt output from the TLC, however, is sensed by the PCL of DMA Channel 1. If an
interrupt operation is used, the DMAC Channel 1 must be configured to interrupt on a
high-to-low transition of the PCL1.
If the DMAC encounters a bus error during operation, a negative transition is caused on the PCL
of Channel 1, thus causing an interrupt.
The GPIB-1014 hardware provides automatic GPIB synchronization after the data transfer is
complete. This allows an interrupt (or a set status bit for polling) when the last data byte has
been transferred and the GPIB is synchronized (that is, all devices on the GPIB have accepted the
last byte). When the DMA transfer is complete and the GPIB is synchronized, a negative
transition is generated on the PCL of Channel 1.
Because the PCL detects a high-to-low transition on its input, the input, once pulled low to
generate an interrupt, must be pulled back to high by your program for the PCL to work properly
on the next transition. For example, if the interrupt of the TLC pulls PCL1 low, your program
must read ISR1 or ISR2 of the TLC to clear the interrupt and pull PCL1 high. If GPIB
synchronization occurs, you must write any value to CFG1 to pull PCL1 high. If a VMEbus
error occurs during a DMA transfer, the PCL1 is pulled high automatically when the VMEbus
memory releases signal BERR* high. Your program cannot pull PCL high in the last case, but
can only clear the PCT bit in the CSR.
Interrupts from the PCL of DMA Channel 1 are enabled by setting the EINT bit in the CCR of
Channel 1. An interrupt is generally not enabled on Channel 0. If triggered, all three interrupt
events mentioned earlier will cause the set PCT bit to indicate a PCL transition and an interrupt.
A bus error that occurs when Channel 1 is active sets both the ERR and PCT bits in the CSR of
Channel 1. A bus error that occurs when Channel 0 is active only sets the PCT bit in the CSR of
Channel 1 and the ERR bit in the CSR of Channel 0.
After an interrupt is generated, the VMEbus interrupt handler asks the interrupting source for a
status/ID byte so that it can branch to the appropriate interrupt service routine. Depending upon
the value of the ERR bit, Channel 1 sends out the Normal Interrupt Vector (NIV) or Error
Interrupt Vector (EIV). Since all errors are logged, it is possible and convenient to use the same
vector for NIV and EIV. The source of the interrupt must be determined by the interrupt service
routine. The status of the TLC interrupt can be found by reading the appropriate TLC status
registers.
The status bits in ISR1 or ISR2 are all automatically cleared when the register is read, even if the
conditions are still true. If two conditions are true at the same time (that is, more than one bit in
ISR1 or ISR2 is set), a software copy of the register must be maintained if the program is going
to analyze the conditions one at a time. Since reading ISR1 can clear the INT bit in ISR2, ISR2
must always be read before ISR1.
The PCL of Channels 0 and 2 are also connected to two GPIB signals so you can directly detect
them. The PCL of Channel 0 is connected to the GPIB Service Request signal (active low). This
can be used to read the status of the SRQ* line at any time or to generate an interrupt when the
SRQ* line is asserted and the TLC is Controller-in-Charge. The PCL of Channel 2 is connected
to the GPIB Remote Enable signal (active low). This can be used to read the status of the REN*
line at any time or to generate an interrupt when the REN* line is asserted.
