Chapter 6
Theory of Operation
© National Instruments Corporation
6-9
GPIB-1014 User Manual
DMA Gating and Control
The DMA Gating and Control circuitry is designed to control the DMA request/acknowledge
interface between the DMAC and the TLC. The circuitry consists of an LS74 flip-flop and
miscellaneous logic gates to generate the DMA request signals (DREQ0* and DREQ1*), the
carry cycle byte (CCBYTE) strobe, and the DMA Acknowledge Enable signal (DACKEN*).
The main function of this circuitry is to gate the DMA request signal from the TLC (DMAREQ)
to the proper DMA channel of the DMAC to perform the carry cycle function. Upon RESET,
the DMA requests from the TLC are directed to Channel 0. This configuration remains
unchanged unless a carry cycle DMA cycle is specified in CFG1 (CC=1). The DMA requests
are gated to Channel 0 until the DMAC DONE* signal is active during a DMA transfer,
indicating that Channel 0 has completely finished (that is, all the blocks in the chain have been
transferred). The circuitry automatically gates the DONE* pulse from Channel 0 to the DMA
request pin (REQ1) of Channel 1, requesting a transfer (DREQ1* is asserted). When the DMAC
answers the request on Channel 1 with ACK1* asserted, CCBYTE is asserted to indicate that the
carry cycle byte transfer is in progress. During the carry cycle byte transfer, signal DACKEN* is
kept high to prevent the circuitry from asserting DMAACK*. In every DMA transfer (except
carry cycle byte transfer), DACKEN* causes DMAACK* to go low to acknowledge a DMA
request from the TLC. The TLC can request DMA during the carry cycle transfer, but will not
be acknowledged until the carry cycle has completed. In addition, since Channel 0 has stopped,
DREQ0* can be asserted by the circuitry but has no effect.
The first byte to be transferred from Channel 1 is the carry cycle byte. This byte must be
transferred by the DMAC to the TLC auxiliary register. Since the TLC does not allow DMA
transfers to the auxiliary register, discrete circuitry must make this cycle appear as a normal write
cycle to the TLC. Furthermore, the circuitry must ensure that this byte is always transferred from
memory to the TLC even though the DMAC may be configured to transfer the data from the
GPIB to VMEbus memory. The circuitry knows that the first byte to be transferred from
Channel 1 is always the carry cycle byte, so when ACK1* is driven low at the start of the DMA
cycle, the onboard signal CCBYTE becomes active. This signal is ORed with the DMAC WR*
signal to ensure that the onboard circuitry performs a read from VMEbus memory and a write to
the TLC.
Signal CCBYTE is also used to gate the TLC register select lines RS2 through RS0 to drive them
as needed to address the TLC auxiliary register, and to drive the TLC CS* line instead of the
DMAACK* line. As mentioned earlier, DACKEN* is kept high during the carry cycle byte to
prevent DMAACK* from asserting. The Timing State Machine circuitry and the TLC interpret
the cycle as a normal write to the TLC, while the VMEbus memory interprets the cycle as a
DMA read from memory. The DMAC signal ACK1* goes high at the end of the transfer. This
low-to-high transition is used to set a flip-flop, which gates further DMA requests from the TLC
to DMAC Channel 1 and disables generation of the CCBYTE signal. When the TLC issues
another DMA request, Channel 1 responds by transferring the last byte of data with a normal
DMA transfer cycle. The low to high transition of ACK1* at the end of this cycle clears the flip-
flop, which masks any further DMA requests from the TLC. Again, the flip-flop state
determines if a carry byte cycle has been completed. It is cleared (Q=0) at all time before and
during the carry cycle byte and set (Q=1) at the end of the carry cycle byte. The output of the
flip-flop is also used to generate signal ALLDONE, which is used in the GPIB synchronization
circuitry (discussed later in this chapter).
