Chapter 6
Theory of Operation
© National Instruments Corporation
6-7
GPIB-1014 User Manual
Configuration Register 2
Four discrete 74LS74A D-type flip-flops are used to implement Configuration Register 2
(CFG2). Data is written into each bit of this register on the rising edge of the WR* signal
generated by the Timing State Machine circuitry. The SC bits are cleared by the onboard
RESET* signal generated by the Clock and Reset circuitry, while the LMR and SFL bits are
cleared only by the VMEbus signal SYSRESET* or by writing to the register. The S/U* bit is
set or cleared (to be in supervisor or slave mode) depending upon the way you have set jumper
W2. This write-only register is used for a variety of configuration functions, including the
following functions:
•
Issuing a Local Master Reset (LMR) to the GPIB-1014. The LMR bit is cleared to a 0 on
SYSRESET*. Writing to CFG2 with this bit set to a 1 drives the GPIB-1014 local signal
RESET*. Writing a 0 to this bit releases RESET.
•
Configuring the GPIB-1014 to be System Controller. Writing a 1 to this bit (SC) configures
the GPIB-1014 as System Controller. This bit is used by the 75162 GPIB control transceiver
to determine whether the GPIB-1014 drives or receives the GPIB signal IFC.
•
Selecting Supervisor-only or User access to the GPIB-1014. A jumper on the GPIB-1014 is
used to automatically determine the state of this bit (SUP) after a system or local reset. After
reset, you can write a 1 to this bit to select Supervisor-only access or a 0 to select User
access.
•
Controlling the GPIB-1014 LED SYSFAIL* indicator. If this bit (SFL) is a 0, the VMEbus
SYSFAIL* line is driven low with an AS756 open collector driver and the LED on the
GPIB-1014 turns red. Writing a 1 to this bit releases the VMEbus SYSFAIL* line and turns
the LED green. This bit is set to 0 on SYSRESET* and is unaffected by a local master reset
(LMR).
Timing State Machine
The Timing State Machine circuitry is designed to control the timing of local signal
LOCAL_DTACK* in slave cycles and the RD* and WR* signals, which control the TLC in
slave and DMA cycles. A 74LS74A flip-flop, two 74LS393 4-bit counters, a 74S139 decoder,
and some miscellaneous logic gates are used to implement a state machine to control this timing.
Slave Cycles
If the GPIB-1014 is functioning as a VMEbus slave, and the DMAC has been addressed, the
VMEbus signal DTACK* is driven by the DMAC, and the timing is controlled entirely by the
DMAC. If the TLC or one of the Configuration Registers has been addressed, however, the
timing is controlled by the state machine.
The timing control begins when one of the signals TLCCS*, CS1*, or CS2* is low, indicating
that the TLC, CFG1, or CFG2 is selected. During a read cycle to the TLC, the TLC RD* signal
is immediately driven low. The circuitry then counts a minimum delay of 250 nsec, which
