National Instruments AT-MIO-64F-5, Руководство пользователя

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Programming Chapter 5
AT-MIO-64F-5 User Manual 5-26 © National Instruments Corporation
Servicing Update Requests
Updating the DACs using a timer signal can be handled using either polled I/O, interrupts or
DMA requests. Upon the application of a falling edge signal to the TMRTRIG* signal, both
DACs are updated and TMRREQ in Status Register 1 is set and if DMA or interrupts are
enabled, a request is generated. TMRTRIG* can be connected to selected internal signals on the
RTSI bus with A4RCV set or the external signal EXTTMRTRIG* with A4RCV cleared. In the
polled I/O mode, the TMRREQ signal must be monitored in the Status Register to determine
when the previous value has been updated to the DAC and a new value is required. The most
desirable solution involves the use of interrupts because the PC is not dedicated to monitoring
the Status Register. If interrupts are enabled, an interrupt occurs when TMRREQ is set. In
interrupt mode, TMRREQ must be cleared using the TMRREQ Clear Register before exiting the
interrupt routine. This clears the interrupt request. The best method of servicing update requests
is with DMA since this is done in parallel with the PC CPU. If DMA is enabled, DMA requests
are generated when TMRREQ is set. When the DMA controller acknowledges the request,
TMRREQ is automatically cleared.
An error is indicated in timer waveform generation when the DACCOMP bit in Status Register 1
is set prematurely. If DACFIFOEF* is clear when another update occurs, then an error has
occurred. This error indicates an underrun condition, where rates are above the maximum rate of
the DMA controller or interrupt handling capabilities. The error condition is cleared by writing
to the TMRREQ Clear Register or the DAC Clear Register.
Programming the Digital I/O Circuitry
The digital input circuitry is controlled and monitored using the Digital Input Register, the
Digital Output Register, and the two bits DIOPAEN and DIOPBEN in Command Register 2.
See the register bit descriptions earlier in this chapter for more information.
To enable digital output port A, set the DIOPAEN bit in Command Register 3. To enable digital
output port B, set the DIOPBEN bit in Command Register 3. When a digital output port is
enabled, the contents of the Digital Output Register are driven onto the digital lines
corresponding to that port. The digital output for both ports A and B are updated by writing the
desired pattern to the Digital Output Register.
In order for an external device to drive the digital I/O lines, the input ports must be enabled.
Clear the DIOPAEN bit in Command Register 3 if an external device is driving digital I/O lines
ADIO<3..0>. Clear the DIOPBEN bit in Command Register 3 if an external device is driving
digital I/O lines BDIO<3..0>. The Digital Input Register can then be read to monitor the state of
the digital I/O lines as driven by the external device.
The logic state of all eight digital I/O lines can be read from the Digital Input Register. If the
digital output ports are enabled, the Digital Input Register serves as a read-back register; that is,
you can determine how the AT-MIO-64F-5 is driving the digital I/O lines by reading the Digital
Input Register.
If any digital I/O line is not driven, it floats to an indeterminate value. If more than one device is
driving any digital I/O line, the voltage at that line may also be indeterminate. In these cases, the
digital line has no meaningful logic value, and reading the Digital Input Register may return
either 1 or 0 for the state of the digital line.