National Instruments AT-MIO-64F-5, Руководство пользователя

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Register Map and Descriptions Chapter 4
AT-MIO-64F-5 User Manual 4-20 © National Instruments Corporation
Bit Name Description (continued)
12 ADCFIFOEF* ADC FIFO Empty Flag Ð This bit reflects the state of the ADC
FIFO. If ADCFIFOEF* is set, one or more A/D conversion results
can be read from the ADC FIFO. If the appropriate conversion
interrupts are enabled, see Table 4-3, and ADCFIFOEF* is set, the
current interrupt indicates that A/D conversion data is available in
the ADC FIFO. To clear the interrupt, the FIFO must be read until
it is empty. If ADCFIFOEF* is cleared, the ADC FIFO is empty
and no conversion interrupt request is asserted.
11 DMATCA DMA Terminal Count Channel A Ð DMATCA reflects the status
of the DMA process on the selected DMA channel A. When the
DMA operation is completed, DMATCA goes high and remains
high until cleared by strobing the DMATCA Clear Register.
10 DMATCB DMA Terminal Count Channel B Ð DMATCB reflects the status
of the DMA process on the selected DMA channel B. When the
DMA operation is completed, DMATCB goes high and remains
high until cleared by strobing the DMATCB Clear Register.
9OVERFLOW Overflow Ð This bit indicates whether the ADC FIFO has
overflowed during a sample run. OVERFLOW is an error
condition that occurs if the FIFO fills up with A/D conversion data
and A/D conversions continue. If OVERFLOW is set, A/D
conversion data has been lost because of FIFO overflow. If
OVERFLOW is clear, no overflow has occurred. If OVERFLOW
occurs during a data acquisition operation, the data acquisition is
terminated immediately. This bit is reset by strobing the DAQ
Clear Register.
8OVERRUN Overrun Ð This bit indicates whether an A/D conversion was
initiated before the previous A/D conversion was complete.
OVERRUN is an error condition that can occur if the data
acquisition sample interval is too small (sample rate is too high).
If OVERRUN is set, one or more conversions were skipped. If
OVERRUN is clear, no overrun condition has occurred. If
OVERRUN occurs during a data acquisition operation, the data
acquisition is immediately terminated. This bit is reset by strobing
the DAQ Clear Register.
7 TMRREQ Timer Request Ð This bit reflects the status of the timer update.
TMRREQ is set whenever the DAC FIFO is ready to receive data,
or a pulse has occurred on the TMRTRIG* signal in the interrupt
mode. TMRREQ generates an interrupt or DMA request only if
the proper mode is selected according to Table 4-3. In DMA
transfer mode, TMRREQ is automatically cleared when the DAC
is written to. In interrupt and programmed I/O modes, TMRREQ
must be cleared by strobing the TMRREQ Clear Register.