National Instruments AT-MIO-64F-5, Руководство пользователя

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Chapter 4 Register Map and Descriptions
© National Instruments Corporation 4-21 AT-MIO-64F-5 User Manual
Bit Name Description (continued)
6 DACCOMP DAC Sequence Complete Ð This bit reflects the status of the DAC
sequence termination circuitry. When the DAC sequence has
normally completed, or ended on an error condition, the
DACCOMP bit is set. If DACCOMP is set prematurely, this
indicates an error condition. If interrupts are enabled, an interrupt
will be generated on this condition. The interrupt is serviced by
strobing the TMRREQ Clear or DAC Clear Register. While the
sequence is in progress, the DACCOMP bit is cleared.
5 DACFIFOFF* DAC FIFO Full Flag Ð This bit reflects the state of the DAC FIFO.
If DACFIFOFF* is clear, the DAC FIFO is full and is not ready to
receive data. If DACFIFOFF* is set, the DAC FIFO is not full and
is able to continue receiving data. If the appropriate DAC and I/O
modes are enabled, interrupts or DMA requests are generated until
the DAC FIFO is full.
4 DACFIFOHF* DAC FIFO Half Full Flag Ð This bit reflects the state of the DAC
FIFO. If DACFIFOHF* is clear, the DAC FIFO is at least half-full
of data. If DACFIFOHF* is set, the DAC FIFO is not half-full of
data. If the appropriate DAC and I/O modes are enabled,
interrupts or DMA requests are generated when the DAC FIFO is
less than half-full.
3 DACFIFOEF* DAC FIFO Empty Flag Ð This bit reflects the state of the DAC
FIFO. If DACFIFOEF* is clear, the DAC FIFO is empty. If
DACFIFOEF* is clear before the last point has been transferred to
the DACs, and DACCOMP is set, this is an error condition and
should be handled appropriately. If DACFIFOEF* is set, then the
DAC FIFO has at least one remaining point to be transferred.
2EEPROMDATA EEPROM Data Ð This bit reflects the value of the data shifted out
of the EEPROM using SCLK with EEPROMCS enabled.
1EEPROMCD* EEPROM Chip Deselect Ð This bit reflects the status of the
EEPROM chip select pin. Because protection circuitry surrounds
the EEPROM, having EEPROMCS enabled in Command
Register 1 does not necessarily result in the EEPROM being
enabled. If EEPROMCD* is low after a mode has been shifted
into the EEPROM, an error occurred in shifting in an unsupported
mode. To initialize EEPROMCD*, EEPROMCS must be brought
low while SCLK is pulsed high.
0 CFGMEMEF* Configuration Memory Empty Flag Ð This bit indicates the status
of the channel configuration memory. If this bit is clear, the
channel configuration memory is empty and can be written to. If
CFGMEMEF* is set, the channel configuration memory is not
empty.