National Instruments AT-MIO-64F-5, Руководство пользователя

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Chapter 4 Register Map and Descriptions
© National Instruments Corporation 4-17 AT-MIO-64F-5 User Manual
Bit Name Description (continued)
13 DAC1DSP DAC 1 DSP Link Enable Ð This bit controls the serial link from
the AT-DSP2200 to DAC 1 of the analog output section. If
DAC1DSP is set, then the serial link is enabled. Data is sent from
the AT-DSP2200 over the RTSI bus and is accepted by DAC 1. If
DAC1DSP is cleared, the serial RTSI link is disabled.
12 DAC0DSP DAC 0 DSP Link Enable Ð This bit controls the serial link from
the AT-DSP2200 to DAC 0 of the analog output section. If
DAC1DSP is set, then the serial link is enabled. Data is sent from
the AT-DSP2200 over the RTSI bus and is accepted by DAC 0. If
DAC1DSP is cleared, the serial RTSI link is disabled.
11-8 DACMB<3..0> DAC Mode Select Ð These bits control the mode used for writing
to and updating the DACs. DACMB3 is used to select the number
of reads from the DAC FIFO per update signal. If DACMB3 is
clear, there will be only one read of the DAC FIFO per update. If
DACMB3 is set, the circuitry will determine whether to perform
one read or two reads from the DAC FIFO depending on the data
in the FIFO. See Table 4-6 for available modes and bit patterns.
Table 4-6. Analog Output Waveform Modes
Waveform Mode
DACMB3 DACMB2 DACMB1 DACMB0
Mode Description
0 0 0 0
Single update with no timed interrupts
1 0 0 0
Single update with timed interrupts
X 0 0 1
DMA access through DAC FIFO (with single
requesting)
X 0 1 0
DMA access through DAC FIFO (with half flag
requesting)
X 0 1 1
FIFO continuous waveform generation (buffer
in DAC FIFO)
X 1 0 0
Programmed cycle waveform generation
(Counter 1 stops after N cycles)
X 1 0 1
Programmed cycle waveform generation
(Counter 2 stops after N cycles)
X 1 1 0
Programmed cycle waveform generation
(Counter 5 stops after N cycles)
X 1 1 1
Pulsed waveform (Counter 1 stops after N
cycles, Counter 2 restarts)
7 DACGATE DAC Update Gate Ð This bit controls the update circuitry for the DACs
in the delayed update mode. If DACGATE is set, updating of the DACs
is inhibited. Values can be directly written to the DAC, but not through
the DAC FIFO. If DACGATE is cleared, updating of and writing to the
DACs proceeds normally.