National Instruments AT-MIO-64F-5, Руководство пользователя

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Theory of Operation Chapter 3
AT-MIO-64F-5 User Manual 3-22 © National Instruments Corporation
A counter can also be active high-level gated by a signal at GATE N+1 and GATE N-1, where N
is the counter number.
The counter generates timing signals at its OUT output pin. The OUT output pin can also be set
to a high-impedance state or a grounded-output state. The counters generate two types of output
signals during counter operation–terminal count pulse output and terminal count toggle output.
Terminal count is often referred to as TC. A counter reaches TC when it counts up or down and
rolls over. In many counter applications, the counter reloads from an internal register when it
reaches TC. In TC pulse output mode, the counter generates a pulse during the cycle that it
reaches TC and reloads. In TC toggle output mode, the counter output changes state after it
reaches TC and reloads. In addition, the counters can be configured for positive logic output or
negative (inverted) logic output for a total of four possible output signals generated for one
timing mode.
The GATE and OUT pins for Counters 1, 2, and 5 and SOURCE pins for Counters 1 and 5 of
the onboard Am9513A are located on the AT-MIO-64F-5 I/O connector. A falling edge signal
on the EXTTRIG* pin of the I/O connector or writing to the STARTDAQ register during a data
acquisition sequence sets the flip-flop output signal connected to the GATE4 input of the
Am9513A and can be used as an additional gate input. This mode is also used in the pretrigger
data acquisition mode. The flip-flop output connected to GATE4 is cleared when the sample
counter reaches TC, when an overflow or overrun occurs, or when the DAQ Clear Register is
written to. An overrun is defined as an error generated when the ADC cannot keep up with its
programmed conversion speed.
The Am9513A SOURCE5 pin is connected to the AT-MIO-64F-5 RTSI switch, which means
that a signal from the RTSI trigger bus can be used as a counting source for the Am9513A
counters.
The Am9513A OUT1, OUT2, OUT3 (EXTCONV*), and OUT5 pins can be used in several
different ways. If waveform generation is enabled, an active low pulse on the output of the
counter selected through the RTSI switch updates the analog output on the two DACs. The
counter outputs can also be used to trigger interrupt and DMA requests. If the proper mode is
selected in Command Register 2, an interrupt or DMA request occurs when a falling edge signal
is detected on the selected DAC update signal.
Counters 3 and 4 of the Am9513A are dedicated to data acquisition timing, and therefore are not
available for general-purpose timing applications. Signals generated at OUT3 and OUT4 are
sent to the data acquisition timing circuitry. GATE3 is controlled by the data acquisition timing
circuitry. OUT3 is internally connected to EXTCONV* so that when internal data acquisition
sequences (OUT3) are used, EXTCONV* should be disconnected or tristated. For the same
reason, if external data acquisition sequences (EXTCONV*) are used, OUT3 should be
programmed to the high-impedance state.
Counter 5 is sometimes used by the data acquisition timing circuitry and concatenated with
Counter 4 to form a 32-bit sample counter. The SCANCLK signal is connected to the
SOURCE3 input of the Am9513A, and OUT1 is sent to the data acquisition timing circuitry.
This allows Counter 1 to be used to divide the SCANCLK signal for generating the
CONFIGCLK signal. See the Data Acquisition Timing Circuitry section earlier in this chapter.
Counter 2 is sometimes used by the data acquisition timing circuitry to assign a time interval to
each cycle through the scan sequence programmed in the channel configuration register. This
mode is called interval channel scanning. See the Multiple-Channel Data Acquisition section
earlier in this chapter.