National Instruments AT-MIO-64F-5, Руководство пользователя

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Configuration and Installation Chapter 2
AT-MIO-64F-5 User Manual 2-24 © National Instruments Corporation
Hence, this noise appears as a differential-mode signal instead of a common-mode signal, and so
the PGIA does not reject it. In this case, instead of directly connecting the negative (-) line to
AIÊGND, connect it to AI GND through a resistor that is about 100 times the equivalent source
impedance. This puts the signal path nearly in balance, so about the same noise couples onto
both (+) and (-) connections, yielding better rejection of electrostatically coupled noise. Also,
this configuration does not load down the source (other than the 100-G
W
input impedance of the
PGIA). You can fully balance the signal path by connecting another resistor of the same value
between the positive (+) input and AI GND. This fully balanced configuration offers slightly
better noise rejection, but has the disadvantage of loading the source down with the series
combination (sum) of the two resistors. If, for instance, the source impedance is 2 k
W
and the
two resistors are each 100 k
W
, the resistors load down the source with 200 k
W
and produce a -
1% gain error.
Both inputs of the PGIA require a DC path to ground in order for the PGIA to work. If the
source is AC coupled (capacitively coupled), then the PGIA needs a resistor between the positive
(+) input and AI GND. If the source has low impedance, choose a resistor that is large enough
not to significantly load the source, but small enough not to produce significant input offset
voltage as a result of input bias current (typically 100 k
W
to 1 M
W
). If the source has high
output impedance, you should balance the signal path (as described above) using the same value
resistor on both the positive (+) and negative (-) inputs, and you should be aware that there is
some gain error from loading down the source.
The PGIA obtains its input DC bias currents from the DC paths to ground. These currents are
typically less than ±200 pA, and do not contribute significantly to error in most applications. If
the source is DC coupled, the resulting DC offset is less than 200 pA times the DC source
resistance. For instance, a 1 k
W
source will produce no more than 0.2 µV of input offset
(0.01 LSB at a gain of 100). If the source is AC coupled, then the resulting DC offset is less than
200 pA times the sum of the two bias resistors. For example, if two 100 k
W
bias resistors are
used, there could be as much as 40 µV of input offset voltage (1.6 LSB at a gain of 100).
Single-Ended Connection Considerations
Single-ended connections are those in which all AT-MIO-64F-5 analog input signals are
referenced to one common ground. The input signals are tied to the positive (+) input of the
PGIA, and their common ground point is tied to the negative (-) input of the PGIA.
When the AT-MIO-64F-5 is configured for single-ended input, up to 64 analog input channels
are available. Single-ended input connections can be used when all input signals meet the
following criteria:
¥ Input signals are high level (greater than 1 V).
¥ Leads connecting the signals to the AT-MIO-64F-5 are less than 15 ft.
¥ All input signals share a common-reference signal (at the source) or are floating.
DIFF input connections are recommended for greater signal integrity if any of the preceding
criteria are not met.