3-50
Falcon ECC Memory Controller Chip Set
3
rom b siz
The rom b siz control bits are the size of ROM/Flash for
Block B. They are encoded as shown in Table 3-16.
Table 3-16. ROM Block B Size Encoding
rom_b_rv
rom_b_rv and rom_a_rv determine which if either of
Blocks A and B is the source of reset vectors or any other
access in the range $FFF00000 - $FFFFFFFF as shown in
Table 3-14.
rom_b_rv is initialized at power-up reset to match the
inverse of the value on the CKD1 pin.
rom b en
When rom b en is set, accesses to Block B ROM/Flash in
the address range selected by ROM B BASE are enabled.
When rom b en is cleared they are disabled.
rom b we
When rom b we is set, writes to Block B ROM/Flash are
enabled. When rom b we is cleared they are disabled.
Refer back to Table 3-15 for more details.
rom b siz
BLOCK
SIZE
%000
1Mbytes
%001
2Mbytes
%010
4Mbytes
%011
8Mbytes
%100
16Mbytes
%101
32Mbytes
%110
64Mbytes
%111
Reserved
Содержание MVME2700 Series
Страница 1: ...MVME2600 2700 Series Single Board Computer Programmer s Reference Guide V2600A PG2 ...
Страница 13: ...xiv ...
Страница 15: ...xvi ...
Страница 67: ...1 50 Board Description and Memory Maps 1 ...
Страница 70: ...Introduction 2 3 2 Four 31 bit tick timers Two 64 bit general purpose registers for cross processor messaging ...
Страница 151: ...2 84 Raven PCI Host Bridge Multi Processor Interrupt Controller Chip 2 ...
Страница 215: ...3 64 Falcon ECC Memory Controller Chip Set 3 ...
Страница 277: ...Glossary GL 14 G L O S S A R Y ...