2-60
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2
Then one of these bits are delivered to each Interrupt Selector. Since this
interrupt source can be multicast, each of these IPR bits must be cleared
separately when the vector is returned for that interrupt to a particular
processor.
If one of the following sets of conditions are true, the interrupt pin for
processor 0 is driven active.
❏
Set1
The source ID in IRR_0 is from an external source.
The destination bit for processor 1 is a 0 for this interrupt.
The priority from IRR_0 is greater than the highest priority in
ISR_0.
The priority from IRR_0 is greater than the contents of task
register_0.
❏
Set2
The source ID in IRR_0 is from an external source.
The destination bit for processor 1 is a 1 for this interrupt.
The source ID in IRR_0 is not present is ISR_1.
The priority from IRR_0 is greater than the highest priority in
ISR_0.
The priority from IRR_0 is greater than the Task Register_0
contents.
The contents of Task Register_0 is less than the contents of Task
Register_1.
❏
Set3
The source ID in IRR_0 is from an internal source.
The priority from IRR_0 is greater than the highest priority in
ISR_0.
The priority from IRR_0 is greater than the Task Register_0
contents.
Содержание MVME2700 Series
Страница 1: ...MVME2600 2700 Series Single Board Computer Programmer s Reference Guide V2600A PG2 ...
Страница 13: ...xiv ...
Страница 15: ...xvi ...
Страница 67: ...1 50 Board Description and Memory Maps 1 ...
Страница 70: ...Introduction 2 3 2 Four 31 bit tick timers Two 64 bit general purpose registers for cross processor messaging ...
Страница 151: ...2 84 Raven PCI Host Bridge Multi Processor Interrupt Controller Chip 2 ...
Страница 215: ...3 64 Falcon ECC Memory Controller Chip Set 3 ...
Страница 277: ...Glossary GL 14 G L O S S A R Y ...