2-72
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2
Timer Destination Registers
This register indicates the destinations for this timer’s interrupts. Timer
interrupts, operate in the Directed delivery interrupt mode. This register
may specify multiple destinations (multicast delivery).
P1
PROCESSOR 1. The interrupt is directed to processor 1.
P0
PROCESSOR 0. The interrupt is directed to processor 0.
External Source Vector/Priority Registers
Offset
Timer 0 - $01130
Timer 1 - $01170
Timer 2 - $011B0
Timer 3 - $011F0
Bit
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Name
TIMER DESTINATION
P1
P0
Operation
R
R
R
R
R/
W
R/W
Reset
$00
$00
$00
$00
0
0
Offset
Int Src 0 - $10000
Int Src 2 -> Int Src15 - $10020 -> $101E0
Bit
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Name
EXTERNAL SOURCE VECTOR/PRIORITY
M
ASK
ACT
PO
L
SENSE
PRIOR
VECTOR
Operation
R/W
R
R
R/W
R/W
R
R
R/W
R
R/W
Reset
1
0
$000
0
0
0
0
$0
$00
$00
Содержание MVME2700 Series
Страница 1: ...MVME2600 2700 Series Single Board Computer Programmer s Reference Guide V2600A PG2 ...
Страница 13: ...xiv ...
Страница 15: ...xvi ...
Страница 67: ...1 50 Board Description and Memory Maps 1 ...
Страница 70: ...Introduction 2 3 2 Four 31 bit tick timers Two 64 bit general purpose registers for cross processor messaging ...
Страница 151: ...2 84 Raven PCI Host Bridge Multi Processor Interrupt Controller Chip 2 ...
Страница 215: ...3 64 Falcon ECC Memory Controller Chip Set 3 ...
Страница 277: ...Glossary GL 14 G L O S S A R Y ...