3-10
Falcon ECC Memory Controller Chip Set
3
Table 3-3. PowerPC 60x Bus to DRAM Access Timing When Configured for
50ns Hyper Devices
Notes:
1. These numbers assume that the PowerPC 60x bus master is doing
address pipelining with TS_ occurring at the minimum time after
AACK_ is asserted. Also the two numbers shown in 1st beat column
are for page hit/page miss.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.
ACCESS TYPE
CLOCK PERIODS REQUIRED FOR:
Total
Clocks
1st
Beat
2nd
Beat
3rd
Beat
4th
Beat
4-Beat Read after Idle (Quad-word
aligned)
8
1
1
1
11
4-Beat Read after Idle (Quad-word
misaligned)
8
2
1
1
12
4-Beat Read after 4-Beat Read
(Quad-word aligned)
5/2
1
1 1
1
8/5
4-Beat Read after 4-Beat Read
(misaligned)
4/2
1
2
1
1
8/6
4-Beat Write after Idle
4
1
1
1
7
4-Beat Write after 4-Beat Write
(Quad-word aligned)
4/3
1
1
1
1
7/6
1-Beat Read after Idle
8
-
-
-
8
1-Beat Read after 1-Beat Read
7/5
1
-
-
-
7/5
1-Beat Write after Idle
4
-
-
-
4
1-Beat Write after 1-Beat Write
9/7
1
-
-
-
9/7
Содержание MVME2700 Series
Страница 1: ...MVME2600 2700 Series Single Board Computer Programmer s Reference Guide V2600A PG2 ...
Страница 13: ...xiv ...
Страница 15: ...xvi ...
Страница 67: ...1 50 Board Description and Memory Maps 1 ...
Страница 70: ...Introduction 2 3 2 Four 31 bit tick timers Two 64 bit general purpose registers for cross processor messaging ...
Страница 151: ...2 84 Raven PCI Host Bridge Multi Processor Interrupt Controller Chip 2 ...
Страница 215: ...3 64 Falcon ECC Memory Controller Chip Set 3 ...
Страница 277: ...Glossary GL 14 G L O S S A R Y ...