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8 MULTIPLE CPU SYSTEM FUNCTIONS
8.4 Data Communication Between CPU Modules
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Communication through direct access (when C Controller module is on the sending side)
When the CPU number-based data assurance is enabled, the data is not assured.
The data is written from the program.
At the multiple CPU synchronous interrupt program (I45) execution, the data is read.
At the multiple CPU synchronous interrupt program (I45) execution, the data is refreshed.
The data read completion from each CPU is notified to the CPU No.1.
CCPU_ToBufHG_ISR( );
Ò
Ó
Õ
Ô
Ó
Ó
Ô
Ô
Õ
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Fixed cycle
communication
area
Device
Device
Device
Device
Without
refresh
function
Programmable controller CPU
(CPU No.2)
Programmable controller CPU
(CPU No.3)
Programmable controller CPU
(CPU No.4)
C Controller module
(CPU No.1)
Fixed cycle
communication
area
Fixed cycle
communication
area
Fixed cycle
communication
area
Содержание MELSEC iQ-R C R12CCPU-V
Страница 1: ...MELSEC iQ R C Controller Module User s Manual Application R12CCPU V ...
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Страница 23: ...1 EXECUTING PROGRAMS 1 3 I O Access Timing 21 1 MEMO ...
Страница 32: ...30 3 MEMORY CONFIGURATION OF C Controller Module 3 4 Files MEMO ...
Страница 257: ...I 255 MEMO ...
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