76
Model
Rated Input Voltage
(23)
AY72 5/12
VDC
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A10
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
Y00
Y10
Y01
Y11
Y02
Y12
Y03
Y13
Y04
Y14
Y05
Y15
Y06
Y16
Y07
Y17
Y08
Y18
Y09
Y19
Y0A
Y1A
Y0B
Y1B
Y0C
Y1C
Y0D
Y1D
Y0E
Y1E
Y0F
Y1F
Vacant
Vacant
Vacant
Vacant
5/12 VDC
0V
5/12 VDC
0V
5/12 VDC
+
−
* The figure above indicates
F
(the first
half 32 points).
The connections for
L
(the latter half
32 points) are the same as for
F
(regard Y00 to Y1F as Y20 to Y3F).
B1
and
B2
, and
A1
and
A2
are connected internally.
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
Y00
Y10
Y01
Y11
Y02
Y12
Y03
Y13
Y04
Y14
Y05
Y15
Y06
Y16
Y07
Y17
Y08
Y18
Y09
Y19
Y0A
Y1A
Y0B
Y1B
Y0C
Y1C
Y0D
Y1D
Y0E
Y1E
Y0F
Y1F
Vacant
Vacant
Vacant
Vacant
5/12 VDC
0V
5/12 VDC
0V
5/12 VDC
+
−
TTL, CMOS logic
Load connection
Содержание Melsec A Series
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