Key Components Description and Operation
UG0617 User Guide Revision 4.0
21
4.8
System Reset
The M2S_RSTB signal (active-low) is generated by the SW7 push-button switch, U35 chip (DS1818), or
U22 chip (TPS3808G09). DEVRST_N is an input-only reset pad that allows assertion of a full reset to the
chip at any time.
DS1818 maintains reset until 150 ms after the 3.3 V supply returns to intolerance. The
TPS3808G09DBVR device monitors the voltage at the VDD_REG terminal. If the voltage at this terminal
sense-drops below the threshold voltage of 0.9 V, the G4M_RSTB signal is asserted.
The following figure shows the system reset interface of the RTG4 Development Board.
Figure 14 •
System Reset Interface
For more information, see the Board Level Schematics document (provided separately).
4.9
Clock Oscillator
A 50 MHz clock oscillator (LVCMOS) with an accuracy of ±50 ppm is available on the board, as listed in
the following table and shown in the following figure. This clock oscillator is connected to the FPGA fabric
to provide a system reference clock.
An on-chip RTG4 PLL can be configured to generate a wide range of high-precision clock frequencies.
Table 10 •
50 MHz Clock
RTG4 Development Kit Pin RTG4 Package Pin Number
RTG4 Device Pin Name
50MHZ_B1
AA39
MSIOD73PB1/GB12_23/CCC_NE0_CLKI2
10K
1 uF
3.3 V
Push button switch
SW7
U35
VDD_REG
U36
Reset
Number
G4M_RSTB
3.3 V
RTG4
DS1818
Reset
TRS3808G09DBVR
Sense
Reset
Number
DEVRST_n
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