Key Components Description and Operation
UG0617 User Guide Revision 4.0
12
4.3
Memory Interface
RTG4 fabric I/Os are provided for the FDRR_E and FDDR_W memories shown in the following figure.
4.3.1
FDDR_E and FDDR_W—DDR3 SDRAM
Each FDDR is provided with four chips of 256 MB DDR3 memory as flexible volatile memory for storing
user data. A chip with 256 MB DDR3 memory is provided for ECC. The single-error correction and
double-error detection (SECDED) feature can be enabled using ECC. The DDR3 interface is
implemented in Bank2.
The following list describes features of the memory interface:
•
MT41K256M8: 32 Meg × 8 × 8 banks
•
Density: 256 MB
•
Clock rate: 333 MHz
•
Data rate: DDR3, 666 MHz
•
Total capacity: 1 GB from four chips
Note:
For more information, see the Board Level Schematics document (provided separately).
The following figure shows the memory interface of the RTG4 Development Board.
Figure 6 •
Memory Interface
Note:
DDR3 chip supports single bit error correction and dual bit error detection.
DDR3 SDRAM 256 MB
256MX8
4 memory chips
and
1 SECDED chip
DDR chips
Data DQ[31:0]
Address A[15:0]
Control lines
CK, CK#
DQS/DQS[3:0]#
DDR3 SDRAM 256 MB
256MX8
4 memory chips
and
1 SECDED chip
DDR chips
Data DQ[31:0]
Address A[15:0]
Control lines
CK, CK#
DQS/DQS[3:0]#
RTG4
FDDR_E – Bank0
FDDR_W – Bank9
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