Key Components Description and Operation
UG0617 User Guide Revision 4.0
19
•
Symmetry: 50% (± 10%)
•
Rise/Fall Time: 1 ns Max—20% to 80% of supply (3.3 V)
•
Output Voltage Levels: 0 = 0.90 minimum, 1.10 typical and 1 = 1.43 typical, 1.60 maximum
•
Differential Output Voltage: 247 mV minimum, 454 mV maximum
The following figure shows the RTG4 Marvell PHY interface.
Figure 11 •
RTG4 Marvell PHY Interface
For more information, see the Board Level Schematics document (provided separately).
4.6
Programming
RTG4 FPGAs support multiple programming interfaces and can address a wide range of platform
requirements. An RTG4 device can be programmed through the JTAG and SPI interfaces.
The dedicated programming SPI port can operate in SPI slave mode.
For more information about SPI programming, see
RTG4 Programming Guide
.
The following figure shows the programming interface of the RTG4 Development Board.
Figure 12 •
Programming Interface
RTG4
Marvell PHY
88E1340S
25 MHz
MDC/ MDIO/ INT/ PHY_RST
C31
G25
G26
C32
RCLK
1
RCLK
2
H2
6
J30
P0_In
3.3 V
1.8 V
MSIO
Lane3/
TXD
RTG4
Level
Translator
Test
Points
Marvell PHY
88E1340S
XTAL_OUT
XTAL_IN
0
1
3
2
P0
Magnetics/
Jack – RJ45
RCLK1
RCLK2
P0_Out
P0_In
SCLK
JTAG
MSIO328NB4/ B32
MSIO/ Bank4
MSIO J26
H26
Lane3/ RXD
Lane3/ TXD
Mux
RTG4
RVI
Header
ETM
Connector
USB Mini-B
Connector
(J47)
FT4232
FP4/FP5
Header
(J22)
Mux
JTAG
(Bank3)
SC_SPI
JTAG_SEL
JTAG
J27
L
L
H H
J32
AD
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