Key Components Description and Operation
UG0617 User Guide Revision 4.0
16
4.4.3
SERDES3 and SERDES4 Interfaces
The SERDES3 and SERDES4 interfaces (lanes 0/1/2/3) are routed to the FMC connector J34.
Reference clocks of the SERDES3 and SERDES4 interfaces are routed from the FMC connector.
The following figure shows the SERDES3 and SERDES4 interfaces of the RTG4 Development Board.
Figure 9 •
SERDES3 and SERDES4 Interfaces
According to the VITA-57 standard, series capacitors should be placed on the daughter board for TXD
and RXD pins.
For more information, see the Board Level Schematics document (provided separately).
SERDES1 Lane0/
RXD
SERDES1 Lane1/
RXD
SERDES1 Lane2/
RXD
SERDES1 Lane3/
RXD
SERDES1 Lane0/
TXD
SERDES1 Lane1/
TXD
SERDES1 Lane2/
TXD
SERDES1 Lane3/
TXD
SERDES2 Lane0/
RXD
SERDES2 Lane1/
RXD
SERDES2 Lane0/
TXD
SERDES2 Lane1/
TXD
SERDES2 Lane2/
TXD
SERDES2 Lane3/
TXD
SERDES2 REFCLK0
FMC
Connector
HPC1
(J34)
SERDES3 Lane0/ RXD
SERDES3 Lane1/ RXD
SERDES3 Lane2/ RXD
SERDES3 Lane3/ RXD
SERDES4 Lane0/ RXD
SERDES4 Lane1/ RXD
SERDES4 Lane2/ RXD
SERDES4 Lane3/ RXD
SERDES3 Lane0/ TXD
SERDES3 Lane1/ TXD
SERDES3 Lane2/ TXD
SERDES3 Lane3/ TXD
SERDES4 Lane0/ TXD
SERDES4 Lane1/ TXD
SERDES4 Lane2/ TXD
SERDES4 Lane3/ TXD
SERDES3 REFCLK0
SERDES4 REFCLK0
RTG4
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