Introduction
UG0617 User Guide Revision 4.0
4
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JTAG programming interface.
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RVI header for application programming and debug.
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FlashPro4 or FlashPro5 programming header and embedded FlashPro5 programmer.
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Dual in-line package (DIP) switches for user application.
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Push-button switches and LEDs for demo purposes.
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Current measurement test points.
The unused MSIO signals are routed to the on-board FMC connectors and unused MSIOD signals are
routed to bread board connector (J10) space.
The following figure shows the RTG4 Development Board.
Figure 2 •
RTG4 Development Board
2.5
Board Key Components
The following table lists key components of the RTG4 Development Board.
Table 2 •
RTG4 Development Board Components
Name
Description
RTG4 FPGA
Microsemi RT4G150 device in a ceramic package with 1,657 pins.
DDR3 synchronous
dynamic random
access memory
(SDRAM)
8 × 256 MB (256 MB Micron DDR3 memories MT41K256M8DA-125 IT:K) for storing data.
2 × 256 MB (512 MB Micron DDR3 memory MT41K256M8DA-125 IT:K) for storing the ECC
bits.
SPI Flash
2 gigabit (2 ×1 Gigabit) SPI flash Micron N25Q00AA13GSF40G chips connected to the MSIO
pins of the RTG4 FPGA.
Ethernet
RJ45 connector (Ethernet jack with magnetics) interfacing with a Marvell 10/100/1000 BASE-T
PHY chip 88E1304S in Serial Gigabit Media Independent Interface (SGMII) mode, interfacing
with the Ethernet port of the RTG4 device (on-chip MAC and external PHY).
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