
Key Components Description and Operation
UG0617 User Guide Revision 4.0
13
4.4
SerDes Interface
The RT4G150 FPGA device on the RTG4 Development Kit has 24 SerDes lanes. The SerDes block can
be accessed using the PCIe edge connector, high-speed SMA connectors, and on-board FMC
connectors.
4.4.1
SERDES PCIe0 Interface
The SERDES PCIe 0 interface (lanes 0/1/2/3) are directly routed to the PCIe connector. The reference
clock is directly routed from the PCIe connector and optionally from the 100 MHz differential clock
source.
The following figure shows the SERDES PCIe0 interface of the RTG4 Development Board.
Figure 7 •
SERDES_PCIe0 Interface
RTG4
SERDES_PCIe0
PCIe Edge
Connector
Lane0/ RXD
Lane1/ RXD
Lane2/ RXD
Lane3/ RXD
Lane0/ TXD
Lane1/ TXD
Lane2/ TXD
Lane3/ TXD
REFCLK0
100 MHz Diff
clock source
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